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Codegen FP select instructions into X86 conditional moves. Annoyingly enough
the X86 does not support a full set of fp cmove instructions, so we can't always fold the condition into the select. :( Yuck. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12577 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -990,10 +990,37 @@ void ISel::emitSelectOperation(MachineBasicBlock *MBB,
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// cmovS
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switch (SelectClass) {
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default:
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case cFP:
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assert(0 && "We don't support floating point selects yet, they should "
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"have been lowered!");
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default: assert(0 && "Unknown value class!");
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case cFP: {
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// Annoyingly, we don't have a full set of floating point conditional
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// moves. :(
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static const unsigned OpcodeTab[2][8] = {
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{ X86::FCMOVNE, X86::FCMOVE, X86::FCMOVAE, X86::FCMOVB,
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X86::FCMOVBE, X86::FCMOVA, 0, 0 },
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{ X86::FCMOVNE, X86::FCMOVE, 0, 0, 0, 0, 0, 0 },
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};
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Opcode = OpcodeTab[isSigned][OpNum];
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// If opcode == 0, we hit a case that we don't support. Output a setcc
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// and compare the result against zero.
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if (Opcode == 0) {
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unsigned CompClass = getClassB(CompTy);
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unsigned CondReg;
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if (CompClass != cLong || OpNum < 2) {
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CondReg = makeAnotherReg(Type::BoolTy);
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// Handle normal comparisons with a setcc instruction...
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BuildMI(*MBB, IP, SetCCOpcodeTab[isSigned][OpNum], 0, CondReg);
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} else {
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// Long comparisons end up in the BL register.
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CondReg = X86::BL;
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}
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// FIXME: Should generate a 'tst r, r'
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BuildMI(*MBB, IP, X86::CMP8ri, 2).addReg(CondReg).addImm(0);
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Opcode = X86::FCMOVE;
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}
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break;
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}
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case cByte:
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case cShort: {
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static const unsigned OpcodeTab[2][8] = {
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@ -1020,20 +1047,15 @@ void ISel::emitSelectOperation(MachineBasicBlock *MBB,
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} else {
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// Get the value being branched on, and use it to set the condition codes.
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unsigned CondReg = getReg(Cond, MBB, IP);
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// FIXME: Should generate a 'tst r, r'
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BuildMI(*MBB, IP, X86::CMP8ri, 2).addReg(CondReg).addImm(0);
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switch (SelectClass) {
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default:
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case cFP:
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assert(0 && "We don't support floating point selects yet, they should "
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"have been lowered!");
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default: assert(0 && "Unknown value class!");
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case cFP: Opcode = X86::FCMOVE; break;
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case cByte:
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case cShort:
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Opcode = X86::CMOVE16rr;
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break;
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case cShort: Opcode = X86::CMOVE16rr; break;
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case cInt:
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case cLong:
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Opcode = X86::CMOVE32rr;
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break;
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case cLong: Opcode = X86::CMOVE32rr; break;
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}
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}
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@ -990,10 +990,37 @@ void ISel::emitSelectOperation(MachineBasicBlock *MBB,
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// cmovS
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switch (SelectClass) {
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default:
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case cFP:
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assert(0 && "We don't support floating point selects yet, they should "
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"have been lowered!");
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default: assert(0 && "Unknown value class!");
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case cFP: {
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// Annoyingly, we don't have a full set of floating point conditional
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// moves. :(
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static const unsigned OpcodeTab[2][8] = {
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{ X86::FCMOVNE, X86::FCMOVE, X86::FCMOVAE, X86::FCMOVB,
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X86::FCMOVBE, X86::FCMOVA, 0, 0 },
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{ X86::FCMOVNE, X86::FCMOVE, 0, 0, 0, 0, 0, 0 },
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};
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Opcode = OpcodeTab[isSigned][OpNum];
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// If opcode == 0, we hit a case that we don't support. Output a setcc
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// and compare the result against zero.
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if (Opcode == 0) {
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unsigned CompClass = getClassB(CompTy);
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unsigned CondReg;
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if (CompClass != cLong || OpNum < 2) {
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CondReg = makeAnotherReg(Type::BoolTy);
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// Handle normal comparisons with a setcc instruction...
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BuildMI(*MBB, IP, SetCCOpcodeTab[isSigned][OpNum], 0, CondReg);
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} else {
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// Long comparisons end up in the BL register.
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CondReg = X86::BL;
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}
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// FIXME: Should generate a 'tst r, r'
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BuildMI(*MBB, IP, X86::CMP8ri, 2).addReg(CondReg).addImm(0);
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Opcode = X86::FCMOVE;
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}
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break;
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}
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case cByte:
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case cShort: {
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static const unsigned OpcodeTab[2][8] = {
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@ -1020,20 +1047,15 @@ void ISel::emitSelectOperation(MachineBasicBlock *MBB,
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} else {
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// Get the value being branched on, and use it to set the condition codes.
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unsigned CondReg = getReg(Cond, MBB, IP);
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// FIXME: Should generate a 'tst r, r'
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BuildMI(*MBB, IP, X86::CMP8ri, 2).addReg(CondReg).addImm(0);
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switch (SelectClass) {
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default:
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case cFP:
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assert(0 && "We don't support floating point selects yet, they should "
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"have been lowered!");
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default: assert(0 && "Unknown value class!");
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case cFP: Opcode = X86::FCMOVE; break;
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case cByte:
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case cShort:
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Opcode = X86::CMOVE16rr;
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break;
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case cShort: Opcode = X86::CMOVE16rr; break;
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case cInt:
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case cLong:
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Opcode = X86::CMOVE32rr;
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break;
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case cLong: Opcode = X86::CMOVE32rr; break;
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}
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}
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