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[mips] Define register class FGRH32 for the high half of the 64-bit floating

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point registers. We will need this register class later when we add
definitions for instructions mfhc1 and mthc1. Also, remove sub-register indices
sub_fpeven and sub_fpodd and use sub_lo and sub_hi instead.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188842 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka
2013-08-20 22:58:56 +00:00
parent 5f560af541
commit 3531db14c6
6 changed files with 60 additions and 16 deletions
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15
lib/Target/Mips/AsmParser/MipsAsmParser.cpp
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@@ -109,6 +109,9 @@ class MipsAsmParser : public MCTargetAsmParser {
MipsAsmParser::OperandMatchResultTy
parseFGR32Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
MipsAsmParser::OperandMatchResultTy
parseFGRH32Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
MipsAsmParser::OperandMatchResultTy
parseFCCRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
@@ -224,6 +227,7 @@ public:
Kind_GPR64,
Kind_HWRegs,
Kind_FGR32Regs,
Kind_FGRH32Regs,
Kind_FGR64Regs,
Kind_AFGR64Regs,
Kind_CCRRegs,
@@ -408,6 +412,10 @@ public:
return (Kind == k_Register) && Reg.Kind == Kind_FGR32Regs;
}
bool isFGRH32Asm() const {
return (Kind == k_Register) && Reg.Kind == Kind_FGRH32Regs;
}
bool isFCCRegsAsm() const {
return (Kind == k_Register) && Reg.Kind == Kind_FCCRegs;
}
@@ -893,6 +901,7 @@ int MipsAsmParser::regKindToRegClass(int RegKind) {
case MipsOperand::Kind_GPR64: return Mips::GPR64RegClassID;
case MipsOperand::Kind_HWRegs: return Mips::HWRegsRegClassID;
case MipsOperand::Kind_FGR32Regs: return Mips::FGR32RegClassID;
case MipsOperand::Kind_FGRH32Regs: return Mips::FGRH32RegClassID;
case MipsOperand::Kind_FGR64Regs: return Mips::FGR64RegClassID;
case MipsOperand::Kind_AFGR64Regs: return Mips::AFGR64RegClassID;
case MipsOperand::Kind_CCRRegs: return Mips::CCRRegClassID;
@@ -1310,6 +1319,7 @@ MipsAsmParser::parseRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
case MipsOperand::Kind_AFGR64Regs:
case MipsOperand::Kind_FGR64Regs:
case MipsOperand::Kind_FGR32Regs:
case MipsOperand::Kind_FGRH32Regs:
RegNum = matchFPURegisterName(RegName);
if (RegKind == MipsOperand::Kind_AFGR64Regs)
RegNum /= 2;
@@ -1415,6 +1425,11 @@ MipsAsmParser::parseFGR32Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
return parseRegs(Operands, (int) MipsOperand::Kind_FGR32Regs);
}
MipsAsmParser::OperandMatchResultTy
MipsAsmParser::parseFGRH32Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
return parseRegs(Operands, (int) MipsOperand::Kind_FGRH32Regs);
}
MipsAsmParser::OperandMatchResultTy
MipsAsmParser::parseFCCRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
return parseRegs(Operands, (int) MipsOperand::Kind_FCCRegs);