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Special case simple binary operator X op C
This avoid generating a register to hold C, which in turn speeds up the register allocator by a lot: ~9% on 164.gzip and ~17% on 256.bzip2. This also speeds up other passes. This also speeds up execution of the program marginally, and makes the asm much easier to read. :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6626 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -983,36 +983,64 @@ void ISel::emitSimpleBinaryOperation(MachineBasicBlock *BB,
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Value *Op0, Value *Op1,
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unsigned OperatorClass,unsigned TargetReg){
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unsigned Class = getClassB(Op0->getType());
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static const unsigned OpcodeTab[][4] = {
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// Arithmetic operators
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{ X86::ADDrr8, X86::ADDrr16, X86::ADDrr32, X86::FpADD }, // ADD
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{ X86::SUBrr8, X86::SUBrr16, X86::SUBrr32, X86::FpSUB }, // SUB
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// Bitwise operators
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{ X86::ANDrr8, X86::ANDrr16, X86::ANDrr32, 0 }, // AND
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{ X86:: ORrr8, X86:: ORrr16, X86:: ORrr32, 0 }, // OR
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{ X86::XORrr8, X86::XORrr16, X86::XORrr32, 0 }, // XOR
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};
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bool isLong = false;
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if (Class == cLong) {
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isLong = true;
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Class = cInt; // Bottom 32 bits are handled just like ints
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}
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unsigned Opcode = OpcodeTab[OperatorClass][Class];
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assert(Opcode && "Floating point arguments to logical inst?");
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unsigned Op0r = getReg(Op0, BB, IP);
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unsigned Op1r = getReg(Op1, BB, IP);
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BMI(BB, IP, Opcode, 2, TargetReg).addReg(Op0r).addReg(Op1r);
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if (isLong) { // Handle the upper 32 bits of long values...
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static const unsigned TopTab[] = {
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X86::ADCrr32, X86::SBBrr32, X86::ANDrr32, X86::ORrr32, X86::XORrr32
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if (!isa<ConstantInt>(Op1) || Class == cLong) {
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static const unsigned OpcodeTab[][4] = {
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// Arithmetic operators
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{ X86::ADDrr8, X86::ADDrr16, X86::ADDrr32, X86::FpADD }, // ADD
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{ X86::SUBrr8, X86::SUBrr16, X86::SUBrr32, X86::FpSUB }, // SUB
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// Bitwise operators
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{ X86::ANDrr8, X86::ANDrr16, X86::ANDrr32, 0 }, // AND
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{ X86:: ORrr8, X86:: ORrr16, X86:: ORrr32, 0 }, // OR
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{ X86::XORrr8, X86::XORrr16, X86::XORrr32, 0 }, // XOR
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};
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BMI(BB, IP, TopTab[OperatorClass], 2,
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TargetReg+1).addReg(Op0r+1).addReg(Op1r+1);
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bool isLong = false;
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if (Class == cLong) {
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isLong = true;
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Class = cInt; // Bottom 32 bits are handled just like ints
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}
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unsigned Opcode = OpcodeTab[OperatorClass][Class];
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assert(Opcode && "Floating point arguments to logical inst?");
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unsigned Op0r = getReg(Op0, BB, IP);
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unsigned Op1r = getReg(Op1, BB, IP);
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BMI(BB, IP, Opcode, 2, TargetReg).addReg(Op0r).addReg(Op1r);
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if (isLong) { // Handle the upper 32 bits of long values...
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static const unsigned TopTab[] = {
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X86::ADCrr32, X86::SBBrr32, X86::ANDrr32, X86::ORrr32, X86::XORrr32
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};
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BMI(BB, IP, TopTab[OperatorClass], 2,
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TargetReg+1).addReg(Op0r+1).addReg(Op1r+1);
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}
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} else {
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// Special case: op Reg, <const>
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ConstantInt *Op1C = cast<ConstantInt>(Op1);
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static const unsigned OpcodeTab[][3] = {
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// Arithmetic operators
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{ X86::ADDri8, X86::ADDri16, X86::ADDri32 }, // ADD
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{ X86::SUBri8, X86::SUBri16, X86::SUBri32 }, // SUB
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// Bitwise operators
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{ X86::ANDri8, X86::ANDri16, X86::ANDri32 }, // AND
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{ X86:: ORri8, X86:: ORri16, X86:: ORri32 }, // OR
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{ X86::XORri8, X86::XORri16, X86::XORri32 }, // XOR
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};
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assert(Class < 3 && "General code handles 64-bit integer types!");
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unsigned Opcode = OpcodeTab[OperatorClass][Class];
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unsigned Op0r = getReg(Op0, BB, IP);
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uint64_t Op1v;
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if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(Op1C))
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Op1v = CSI->getValue();
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else
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Op1v = cast<ConstantUInt>(Op1C)->getValue();
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// Mask off any upper bits of the constant, if there are any...
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Op1v &= (1ULL << (8 << Class)) - 1;
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BMI(BB, IP, Opcode, 2, TargetReg).addReg(Op0r).addZImm(Op1v);
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}
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}
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@ -983,36 +983,64 @@ void ISel::emitSimpleBinaryOperation(MachineBasicBlock *BB,
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Value *Op0, Value *Op1,
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unsigned OperatorClass,unsigned TargetReg){
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unsigned Class = getClassB(Op0->getType());
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static const unsigned OpcodeTab[][4] = {
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// Arithmetic operators
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{ X86::ADDrr8, X86::ADDrr16, X86::ADDrr32, X86::FpADD }, // ADD
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{ X86::SUBrr8, X86::SUBrr16, X86::SUBrr32, X86::FpSUB }, // SUB
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// Bitwise operators
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{ X86::ANDrr8, X86::ANDrr16, X86::ANDrr32, 0 }, // AND
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{ X86:: ORrr8, X86:: ORrr16, X86:: ORrr32, 0 }, // OR
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{ X86::XORrr8, X86::XORrr16, X86::XORrr32, 0 }, // XOR
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};
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bool isLong = false;
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if (Class == cLong) {
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isLong = true;
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Class = cInt; // Bottom 32 bits are handled just like ints
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}
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unsigned Opcode = OpcodeTab[OperatorClass][Class];
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assert(Opcode && "Floating point arguments to logical inst?");
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unsigned Op0r = getReg(Op0, BB, IP);
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unsigned Op1r = getReg(Op1, BB, IP);
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BMI(BB, IP, Opcode, 2, TargetReg).addReg(Op0r).addReg(Op1r);
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if (isLong) { // Handle the upper 32 bits of long values...
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static const unsigned TopTab[] = {
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X86::ADCrr32, X86::SBBrr32, X86::ANDrr32, X86::ORrr32, X86::XORrr32
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if (!isa<ConstantInt>(Op1) || Class == cLong) {
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static const unsigned OpcodeTab[][4] = {
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// Arithmetic operators
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{ X86::ADDrr8, X86::ADDrr16, X86::ADDrr32, X86::FpADD }, // ADD
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{ X86::SUBrr8, X86::SUBrr16, X86::SUBrr32, X86::FpSUB }, // SUB
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// Bitwise operators
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{ X86::ANDrr8, X86::ANDrr16, X86::ANDrr32, 0 }, // AND
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{ X86:: ORrr8, X86:: ORrr16, X86:: ORrr32, 0 }, // OR
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{ X86::XORrr8, X86::XORrr16, X86::XORrr32, 0 }, // XOR
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};
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BMI(BB, IP, TopTab[OperatorClass], 2,
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TargetReg+1).addReg(Op0r+1).addReg(Op1r+1);
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bool isLong = false;
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if (Class == cLong) {
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isLong = true;
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Class = cInt; // Bottom 32 bits are handled just like ints
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}
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unsigned Opcode = OpcodeTab[OperatorClass][Class];
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assert(Opcode && "Floating point arguments to logical inst?");
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unsigned Op0r = getReg(Op0, BB, IP);
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unsigned Op1r = getReg(Op1, BB, IP);
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BMI(BB, IP, Opcode, 2, TargetReg).addReg(Op0r).addReg(Op1r);
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if (isLong) { // Handle the upper 32 bits of long values...
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static const unsigned TopTab[] = {
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X86::ADCrr32, X86::SBBrr32, X86::ANDrr32, X86::ORrr32, X86::XORrr32
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};
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BMI(BB, IP, TopTab[OperatorClass], 2,
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TargetReg+1).addReg(Op0r+1).addReg(Op1r+1);
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}
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} else {
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// Special case: op Reg, <const>
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ConstantInt *Op1C = cast<ConstantInt>(Op1);
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static const unsigned OpcodeTab[][3] = {
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// Arithmetic operators
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{ X86::ADDri8, X86::ADDri16, X86::ADDri32 }, // ADD
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{ X86::SUBri8, X86::SUBri16, X86::SUBri32 }, // SUB
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// Bitwise operators
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{ X86::ANDri8, X86::ANDri16, X86::ANDri32 }, // AND
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{ X86:: ORri8, X86:: ORri16, X86:: ORri32 }, // OR
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{ X86::XORri8, X86::XORri16, X86::XORri32 }, // XOR
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};
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assert(Class < 3 && "General code handles 64-bit integer types!");
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unsigned Opcode = OpcodeTab[OperatorClass][Class];
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unsigned Op0r = getReg(Op0, BB, IP);
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uint64_t Op1v;
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if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(Op1C))
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Op1v = CSI->getValue();
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else
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Op1v = cast<ConstantUInt>(Op1C)->getValue();
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// Mask off any upper bits of the constant, if there are any...
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Op1v &= (1ULL << (8 << Class)) - 1;
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BMI(BB, IP, Opcode, 2, TargetReg).addReg(Op0r).addZImm(Op1v);
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}
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}
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