From 353dea2f0aca7ddbdad242b9dabb065337744d98 Mon Sep 17 00:00:00 2001 From: Bill Wendling Date: Sun, 31 Aug 2008 01:04:56 +0000 Subject: [PATCH] For this pattern, ROTR is the cheaper option. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55576 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index c0d5d08df12..2521609f5b6 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -2075,14 +2075,14 @@ SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS) { } } else if (LExtOp0.getOpcode() == ISD::SUB && RExtOp0 == LExtOp0.getOperand(1)) { - // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> + // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> // (rotr x, y) - // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> + // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> // (rotl x, (sub 32, y)) if (ConstantSDNode *SUBC = cast(LExtOp0.getOperand(0))) { if (SUBC->getAPIntValue() == OpSizeInBits) { - return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, VT, LHSShiftArg, - HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); + return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, VT, LHSShiftArg, + HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); } } }