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For this pattern, ROTR is the cheaper option.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55576 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2075,14 +2075,14 @@ SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS) {
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}
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}
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} else if (LExtOp0.getOpcode() == ISD::SUB &&
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} else if (LExtOp0.getOpcode() == ISD::SUB &&
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RExtOp0 == LExtOp0.getOperand(1)) {
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RExtOp0 == LExtOp0.getOperand(1)) {
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// fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) ->
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// fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
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// (rotr x, y)
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// (rotr x, y)
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// fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) ->
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// fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
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// (rotl x, (sub 32, y))
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// (rotl x, (sub 32, y))
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if (ConstantSDNode *SUBC = cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
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if (ConstantSDNode *SUBC = cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
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if (SUBC->getAPIntValue() == OpSizeInBits) {
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if (SUBC->getAPIntValue() == OpSizeInBits) {
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return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, VT, LHSShiftArg,
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return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, VT, LHSShiftArg,
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HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode();
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HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode();
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}
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}
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}
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}
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}
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}
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