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Fix the bug where the immediate shift amount for Thumb logical shift instructions are incorrectly disassembled.

Browse Source 
rdar://problem/9266265


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129298 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen 2011-04-11 21:14:35 +00:00
parent d67705faaa
commit 35563fee7b
2 changed files with 23 additions and 6 deletions
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23
lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
View File

@ -398,9 +398,17 @@ static bool DisassembleThumb1General(MCInst &MI, unsigned Opcode, uint32_t insn,
assert(OpInfo[OpIdx].RegClass < 0 &&
!OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()
&& "Pure imm operand expected");
MI.addOperand(MCOperand::CreateImm(UseRt ? getT1Imm8(insn)
: (Imm3 ? getT1Imm3(insn)
: getT1Imm5(insn))));
unsigned Imm = 0;
if (UseRt)
Imm = getT1Imm8(insn);
else if (Imm3)
Imm = getT1Imm3(insn);
else {
Imm = getT1Imm5(insn);
ARM_AM::ShiftOpc ShOp = getShiftOpcForBits(slice(insn, 12, 11));
getImmShiftSE(ShOp, Imm);
}
MI.addOperand(MCOperand::CreateImm(Imm));
}
++OpIdx;
@ -1385,9 +1393,12 @@ static bool DisassembleThumb2DPSoReg(MCInst &MI, unsigned Opcode, uint32_t insn,
if (OpInfo[OpIdx].RegClass < 0 && !OpInfo[OpIdx].isPredicate()
&& !OpInfo[OpIdx].isOptionalDef()) {
if (Thumb2ShiftOpcode(Opcode))
MI.addOperand(MCOperand::CreateImm(getShiftAmtBits(insn)));
else {
if (Thumb2ShiftOpcode(Opcode)) {
unsigned Imm = getShiftAmtBits(insn);
ARM_AM::ShiftOpc ShOp = getShiftOpcForBits(slice(insn, 5, 4));
getImmShiftSE(ShOp, Imm);
MI.addOperand(MCOperand::CreateImm(Imm));
} else {
// Build the constant shift specifier operand.
unsigned bits2 = getShiftTypeBits(insn);
unsigned imm5 = getShiftAmtBits(insn);

6
test/MC/Disassembler/ARM/thumb-tests.txt
View File

@ -208,3 +208,9 @@
# CHECK: isb
0xbf 0xf3 0x6f 0x8f
# CHECK: asrs r1, r0, #32
0x1 0x10
# CHECK: lsr.w r10, r0, #32
0x4f 0xea 0x10 0x0a