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Fix the bug where the immediate shift amount for Thumb logical shift instructions are incorrectly disassembled.
rdar://problem/9266265 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129298 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -398,9 +398,17 @@ static bool DisassembleThumb1General(MCInst &MI, unsigned Opcode, uint32_t insn,
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assert(OpInfo[OpIdx].RegClass < 0 &&
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assert(OpInfo[OpIdx].RegClass < 0 &&
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!OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()
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!OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()
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&& "Pure imm operand expected");
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&& "Pure imm operand expected");
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MI.addOperand(MCOperand::CreateImm(UseRt ? getT1Imm8(insn)
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unsigned Imm = 0;
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: (Imm3 ? getT1Imm3(insn)
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if (UseRt)
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: getT1Imm5(insn))));
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Imm = getT1Imm8(insn);
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else if (Imm3)
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Imm = getT1Imm3(insn);
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else {
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Imm = getT1Imm5(insn);
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ARM_AM::ShiftOpc ShOp = getShiftOpcForBits(slice(insn, 12, 11));
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getImmShiftSE(ShOp, Imm);
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}
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MI.addOperand(MCOperand::CreateImm(Imm));
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}
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}
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++OpIdx;
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++OpIdx;
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@ -1385,9 +1393,12 @@ static bool DisassembleThumb2DPSoReg(MCInst &MI, unsigned Opcode, uint32_t insn,
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if (OpInfo[OpIdx].RegClass < 0 && !OpInfo[OpIdx].isPredicate()
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if (OpInfo[OpIdx].RegClass < 0 && !OpInfo[OpIdx].isPredicate()
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&& !OpInfo[OpIdx].isOptionalDef()) {
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&& !OpInfo[OpIdx].isOptionalDef()) {
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if (Thumb2ShiftOpcode(Opcode))
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if (Thumb2ShiftOpcode(Opcode)) {
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MI.addOperand(MCOperand::CreateImm(getShiftAmtBits(insn)));
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unsigned Imm = getShiftAmtBits(insn);
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else {
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ARM_AM::ShiftOpc ShOp = getShiftOpcForBits(slice(insn, 5, 4));
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getImmShiftSE(ShOp, Imm);
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MI.addOperand(MCOperand::CreateImm(Imm));
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} else {
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// Build the constant shift specifier operand.
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// Build the constant shift specifier operand.
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unsigned bits2 = getShiftTypeBits(insn);
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unsigned bits2 = getShiftTypeBits(insn);
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unsigned imm5 = getShiftAmtBits(insn);
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unsigned imm5 = getShiftAmtBits(insn);
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@ -208,3 +208,9 @@
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# CHECK: isb
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# CHECK: isb
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0xbf 0xf3 0x6f 0x8f
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0xbf 0xf3 0x6f 0x8f
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# CHECK: asrs r1, r0, #32
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0x1 0x10
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# CHECK: lsr.w r10, r0, #32
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0x4f 0xea 0x10 0x0a
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