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initial prologue and epilogue implementation. Need to define add and sub before finishing it :-)

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29175 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Rafael Espindola 2006-07-18 17:00:30 +00:00
parent 303c695529
commit 355746359e
2 changed files with 23 additions and 1 deletions
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4
lib/Target/ARM/ARMInstrInfo.td
View File

@ -53,7 +53,9 @@ def ADJCALLSTACKDOWN : InstARM<(ops i32imm:$amt),
"!ADJCALLSTACKDOWN $amt",
[(callseq_start imm:$amt)]>;
def bxr: InstARM<(ops IntRegs:$dst), "bx $dst", [(brind IntRegs:$dst)]>;
let isReturn = 1 in {
def bx: InstARM<(ops IntRegs:$dst), "bx $dst", [(brind IntRegs:$dst)]>;
}
def bl: InstARM<(ops i32imm:$func, variable_ops), "bl $func", [(ARMcall tglobaladdr:$func)]>;

20
lib/Target/ARM/ARMRegisterInfo.cpp
View File

@ -116,10 +116,30 @@ void ARMRegisterInfo::
processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
MachineBasicBlock &MBB = MF.front();
MachineFrameInfo *MFI = MF.getFrameInfo();
int NumBytes = (int) MFI->getStackSize();
//hack
assert(NumBytes == 0);
//add a sp = sp - 4
BuildMI(MBB, MBB.begin(), ARM::str, 1, ARM::R14).addReg(ARM::R13);
}
void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
MachineBasicBlock::iterator MBBI = prior(MBB.end());
assert(MBBI->getOpcode() == ARM::bx &&
"Can only insert epilog into returning blocks");
MachineFrameInfo *MFI = MF.getFrameInfo();
int NumBytes = (int) MFI->getStackSize();
//hack
assert(NumBytes == 0);
BuildMI(MBB, MBBI, ARM::ldr, 2, ARM::R14).addImm(0).addReg(ARM::R13);
//add a sp = sp + 4
}
unsigned ARMRegisterInfo::getRARegister() const {