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Add workaround for Cortex-M3 errata 602117 by replacing ldrd x, y, [x] with ldm or ldr pairs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144123 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -62,6 +62,7 @@ namespace {
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const TargetInstrInfo *TII;
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const TargetInstrInfo *TII;
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const TargetRegisterInfo *TRI;
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const TargetRegisterInfo *TRI;
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const ARMSubtarget *STI;
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ARMFunctionInfo *AFI;
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ARMFunctionInfo *AFI;
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RegScavenger *RS;
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RegScavenger *RS;
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bool isThumb2;
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bool isThumb2;
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@ -1071,11 +1072,17 @@ bool ARMLoadStoreOpt::FixInvalidRegPairOp(MachineBasicBlock &MBB,
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unsigned Opcode = MI->getOpcode();
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unsigned Opcode = MI->getOpcode();
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if (Opcode == ARM::LDRD || Opcode == ARM::STRD ||
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if (Opcode == ARM::LDRD || Opcode == ARM::STRD ||
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Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8) {
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Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8) {
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const MachineOperand &BaseOp = MI->getOperand(2);
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unsigned BaseReg = BaseOp.getReg();
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unsigned EvenReg = MI->getOperand(0).getReg();
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unsigned EvenReg = MI->getOperand(0).getReg();
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unsigned OddReg = MI->getOperand(1).getReg();
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unsigned OddReg = MI->getOperand(1).getReg();
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unsigned EvenRegNum = TRI->getDwarfRegNum(EvenReg, false);
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unsigned EvenRegNum = TRI->getDwarfRegNum(EvenReg, false);
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unsigned OddRegNum = TRI->getDwarfRegNum(OddReg, false);
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unsigned OddRegNum = TRI->getDwarfRegNum(OddReg, false);
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if ((EvenRegNum & 1) == 0 && (EvenRegNum + 1) == OddRegNum)
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// ARM errata 602117: LDRD with base in list may result in incorrect base
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// register when interrupted or faulted.
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bool Errata602117 = EvenReg == BaseReg && STI->getCPUString() == "cortex-m3";
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if (!Errata602117 &&
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((EvenRegNum & 1) == 0 && (EvenRegNum + 1) == OddRegNum))
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return false;
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return false;
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MachineBasicBlock::iterator NewBBI = MBBI;
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MachineBasicBlock::iterator NewBBI = MBBI;
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@ -1087,8 +1094,6 @@ bool ARMLoadStoreOpt::FixInvalidRegPairOp(MachineBasicBlock &MBB,
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bool OddDeadKill = isLd ?
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bool OddDeadKill = isLd ?
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MI->getOperand(1).isDead() : MI->getOperand(1).isKill();
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MI->getOperand(1).isDead() : MI->getOperand(1).isKill();
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bool OddUndef = MI->getOperand(1).isUndef();
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bool OddUndef = MI->getOperand(1).isUndef();
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const MachineOperand &BaseOp = MI->getOperand(2);
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unsigned BaseReg = BaseOp.getReg();
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bool BaseKill = BaseOp.isKill();
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bool BaseKill = BaseOp.isKill();
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bool BaseUndef = BaseOp.isUndef();
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bool BaseUndef = BaseOp.isUndef();
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bool OffKill = isT2 ? false : MI->getOperand(3).isKill();
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bool OffKill = isT2 ? false : MI->getOperand(3).isKill();
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@ -1380,6 +1385,7 @@ bool ARMLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
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AFI = Fn.getInfo<ARMFunctionInfo>();
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AFI = Fn.getInfo<ARMFunctionInfo>();
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TII = TM.getInstrInfo();
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TII = TM.getInstrInfo();
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TRI = TM.getRegisterInfo();
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TRI = TM.getRegisterInfo();
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STI = &TM.getSubtarget<ARMSubtarget>();
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RS = new RegScavenger();
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RS = new RegScavenger();
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isThumb2 = AFI->isThumb2Function();
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isThumb2 = AFI->isThumb2Function();
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@ -1,21 +1,22 @@
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; RUN: llc < %s -mtriple=armv6-apple-darwin -regalloc=linearscan | FileCheck %s -check-prefix=V6
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; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 -regalloc=fast | FileCheck %s -check-prefix=A8
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; RUN: llc < %s -mtriple=armv5-apple-darwin -regalloc=linearscan | FileCheck %s -check-prefix=V5
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; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-m3 -regalloc=fast | FileCheck %s -check-prefix=M3
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; RUN: llc < %s -mtriple=armv6-eabi -regalloc=linearscan | FileCheck %s -check-prefix=EABI
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; rdar://6949835
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; rdar://r6949835
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; Magic ARM pair hints works best with linearscan.
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; Magic ARM pair hints works best with linearscan / fast.
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; Cortex-M3 errata 602117: LDRD with base in list may result in incorrect base
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; register when interrupted or faulted.
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@b = external global i64*
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@b = external global i64*
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define i64 @t(i64 %a) nounwind readonly {
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define i64 @t(i64 %a) nounwind readonly {
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entry:
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entry:
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;V6: ldrd r2, r3, [r2]
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; A8: t:
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; A8: ldrd r2, r3, [r2]
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;V5: ldr r{{[0-9]+}}, [r2]
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; M3: t:
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;V5: ldr r{{[0-9]+}}, [r2, #4]
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; M3-NOT: ldrd
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; M3: ldm.w r2, {r2, r3}
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;EABI: ldr r{{[0-9]+}}, [r2]
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;EABI: ldr r{{[0-9]+}}, [r2, #4]
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%0 = load i64** @b, align 4
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%0 = load i64** @b, align 4
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%1 = load i64* %0, align 4
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%1 = load i64* %0, align 4
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