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https://github.com/c64scene-ar/llvm-6502.git
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InstCombine: simplify comparisons to zero of (shl %x, Cst) or (mul %x, Cst)
This simplification happens at 2 places : - using the nsw attribute when the shl / mul is used by a sign test - when the shl / mul is compared for (in)equality to zero git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177856 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -139,6 +139,42 @@ static bool isSignBitCheck(ICmpInst::Predicate pred, ConstantInt *RHS,
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}
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}
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/// Returns true if the exploded icmp can be expressed as a comparison to zero
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/// and update the predicate accordingly. The signedness of the comparison is
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static bool isSignTest(ICmpInst::Predicate &pred, const ConstantInt *RHS) {
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if (!ICmpInst::isSigned(pred))
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return false;
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if (RHS->isZero())
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return true;
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if (RHS->isOne())
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switch (pred) {
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case ICmpInst::ICMP_SGE:
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pred = ICmpInst::ICMP_SGT;
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return true;
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case ICmpInst::ICMP_SLT:
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pred = ICmpInst::ICMP_SLE;
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return true;
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default:
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return false;
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}
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if (RHS->isAllOnesValue())
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switch (pred) {
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case ICmpInst::ICMP_SLE:
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pred = ICmpInst::ICMP_SLT;
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return true;
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case ICmpInst::ICMP_SGT:
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pred = ICmpInst::ICMP_SGE;
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return true;
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default:
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return false;
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}
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return false;
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}
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// isHighOnes - Return true if the constant is of the form 1+0+.
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// This is the same as lowones(~X).
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static bool isHighOnes(const ConstantInt *CI) {
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@ -1282,6 +1318,25 @@ Instruction *InstCombiner::visitICmpInstWithInstAndIntCst(ICmpInst &ICI,
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break;
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}
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case Instruction::Mul: { // (icmp pred (mul X, Val), CI)
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ConstantInt *Val = dyn_cast<ConstantInt>(LHSI->getOperand(1));
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if (!Val) break;
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if (!ICI.isEquality()) {
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// If this is a signed comparison to 0 and the mul is sign preserving,
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// use the mul LHS operand instead.
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ICmpInst::Predicate pred = ICI.getPredicate();
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if (isSignTest(pred, RHS) && !Val->isZero() &&
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cast<BinaryOperator>(LHSI)->hasNoSignedWrap())
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return new ICmpInst(Val->isNegative() ?
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ICmpInst::getSwappedPredicate(pred) : pred,
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LHSI->getOperand(0),
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Constant::getNullValue(RHS->getType()));
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}
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break;
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}
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case Instruction::Shl: { // (icmp pred (shl X, ShAmt), CI)
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ConstantInt *ShAmt = dyn_cast<ConstantInt>(LHSI->getOperand(1));
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if (!ShAmt) break;
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@ -1313,6 +1368,12 @@ Instruction *InstCombiner::visitICmpInstWithInstAndIntCst(ICmpInst &ICI,
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return new ICmpInst(ICI.getPredicate(), LHSI->getOperand(0),
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ConstantExpr::getLShr(RHS, ShAmt));
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// If the shift is NSW and we compare to 0, then it is just shifting out
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// sign bits, no need for an AND either.
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if (cast<BinaryOperator>(LHSI)->hasNoSignedWrap() && RHSV == 0)
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return new ICmpInst(ICI.getPredicate(), LHSI->getOperand(0),
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ConstantExpr::getLShr(RHS, ShAmt));
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if (LHSI->hasOneUse()) {
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// Otherwise strength reduce the shift into an and.
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uint32_t ShAmtVal = (uint32_t)ShAmt->getLimitedValue(TypeBits);
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@ -1327,6 +1388,15 @@ Instruction *InstCombiner::visitICmpInstWithInstAndIntCst(ICmpInst &ICI,
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}
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}
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// If this is a signed comparison to 0 and the shift is sign preserving,
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// use the shift LHS operand instead.
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ICmpInst::Predicate pred = ICI.getPredicate();
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if (isSignTest(pred, RHS) &&
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cast<BinaryOperator>(LHSI)->hasNoSignedWrap())
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return new ICmpInst(pred,
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LHSI->getOperand(0),
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Constant::getNullValue(RHS->getType()));
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// Otherwise, if this is a comparison of the sign bit, simplify to and/test.
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bool TrueIfSigned = false;
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if (LHSI->hasOneUse() &&
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@ -1541,6 +1611,19 @@ Instruction *InstCombiner::visitICmpInstWithInstAndIntCst(ICmpInst &ICI,
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return new ICmpInst(pred, X, NegX);
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}
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}
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break;
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case Instruction::Mul:
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if (RHSV == 0) {
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if (ConstantInt *BOC = dyn_cast<ConstantInt>(BO->getOperand(1))) {
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// The trivial case (mul X, 0) is handled by InstSimplify
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// General case : (mul X, C) != 0 iff X != 0
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// (mul X, C) == 0 iff X == 0
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if (!BOC->isZero())
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return new ICmpInst(ICI.getPredicate(), BO->getOperand(0),
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Constant::getNullValue(RHS->getType()));
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}
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}
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break;
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default: break;
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}
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} else if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(LHSI)) {
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@ -744,3 +744,145 @@ define i1 @icmp_shl24(i32 %x) {
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%cmp = icmp slt i32 %shl, 603979776
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ret i1 %cmp
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}
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; If the (shl x, C) preserved the sign and this is a sign test,
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; compare the LHS operand instead
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; CHECK: @icmp_shl_nsw_sgt
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; CHECK-NEXT: icmp sgt i32 %x, 0
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define i1 @icmp_shl_nsw_sgt(i32 %x) {
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%shl = shl nsw i32 %x, 21
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%cmp = icmp sgt i32 %shl, 0
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ret i1 %cmp
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}
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; CHECK: @icmp_shl_nsw_sge0
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; CHECK-NEXT: icmp sgt i32 %x, -1
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define i1 @icmp_shl_nsw_sge0(i32 %x) {
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%shl = shl nsw i32 %x, 21
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%cmp = icmp sge i32 %shl, 0
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ret i1 %cmp
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}
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; CHECK: @icmp_shl_nsw_sge1
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; CHECK-NEXT: icmp sgt i32 %x, 0
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define i1 @icmp_shl_nsw_sge1(i32 %x) {
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%shl = shl nsw i32 %x, 21
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%cmp = icmp sge i32 %shl, 1
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ret i1 %cmp
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}
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; Checks for icmp (eq|ne) (shl x, C), 0
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; CHECK: @icmp_shl_nsw_eq
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; CHECK-NEXT: icmp eq i32 %x, 0
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define i1 @icmp_shl_nsw_eq(i32 %x) {
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%mul = shl nsw i32 %x, 5
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%cmp = icmp eq i32 %mul, 0
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ret i1 %cmp
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}
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; CHECK: @icmp_shl_eq
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; CHECK-NOT: icmp eq i32 %mul, 0
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define i1 @icmp_shl_eq(i32 %x) {
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%mul = shl i32 %x, 5
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%cmp = icmp eq i32 %mul, 0
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ret i1 %cmp
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}
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; CHECK: @icmp_shl_nsw_ne
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; CHECK-NEXT: icmp ne i32 %x, 0
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define i1 @icmp_shl_nsw_ne(i32 %x) {
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%mul = shl nsw i32 %x, 7
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%cmp = icmp ne i32 %mul, 0
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ret i1 %cmp
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}
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; CHECK: @icmp_shl_ne
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; CHECK-NOT: icmp ne i32 %x, 0
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define i1 @icmp_shl_ne(i32 %x) {
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%mul = shl i32 %x, 7
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%cmp = icmp ne i32 %mul, 0
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ret i1 %cmp
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}
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; If the (mul x, C) preserved the sign and this is sign test,
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; compare the LHS operand instead
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; CHECK: @icmp_mul_nsw
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; CHECK-NEXT: icmp sgt i32 %x, 0
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define i1 @icmp_mul_nsw(i32 %x) {
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%mul = mul nsw i32 %x, 12
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%cmp = icmp sgt i32 %mul, 0
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ret i1 %cmp
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}
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; CHECK: @icmp_mul_nsw1
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; CHECK-NEXT: icmp slt i32 %x, 0
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define i1 @icmp_mul_nsw1(i32 %x) {
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%mul = mul nsw i32 %x, 12
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%cmp = icmp sle i32 %mul, -1
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ret i1 %cmp
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}
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; CHECK: @icmp_mul_nsw_neg
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; CHECK-NEXT: icmp slt i32 %x, 1
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define i1 @icmp_mul_nsw_neg(i32 %x) {
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%mul = mul nsw i32 %x, -12
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%cmp = icmp sge i32 %mul, 0
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ret i1 %cmp
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}
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; CHECK: @icmp_mul_nsw_neg1
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; CHECK-NEXT: icmp slt i32 %x, 0
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define i1 @icmp_mul_nsw_neg1(i32 %x) {
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%mul = mul nsw i32 %x, -12
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%cmp = icmp sge i32 %mul, 1
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ret i1 %cmp
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}
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; CHECK: @icmp_mul_nsw_0
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; CHECK-NOT: icmp sgt i32 %x, 0
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define i1 @icmp_mul_nsw_0(i32 %x) {
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%mul = mul nsw i32 %x, 0
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%cmp = icmp sgt i32 %mul, 0
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ret i1 %cmp
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}
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; CHECK: @icmp_mul
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; CHECK-NEXT: %mul = mul i32 %x, -12
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define i1 @icmp_mul(i32 %x) {
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%mul = mul i32 %x, -12
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%cmp = icmp sge i32 %mul, 0
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ret i1 %cmp
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}
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; Checks for icmp (eq|ne) (mul x, C), 0
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; CHECK: @icmp_mul_neq0
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; CHECK-NEXT: icmp ne i32 %x, 0
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define i1 @icmp_mul_neq0(i32 %x) {
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%mul = mul i32 %x, -12
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%cmp = icmp ne i32 %mul, 0
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ret i1 %cmp
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}
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; CHECK: @icmp_mul_eq0
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; CHECK-NEXT: icmp eq i32 %x, 0
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define i1 @icmp_mul_eq0(i32 %x) {
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%mul = mul i32 %x, 12
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%cmp = icmp eq i32 %mul, 0
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ret i1 %cmp
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}
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; CHECK: @icmp_mul0_eq0
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; CHECK-NEXT: ret i1 true
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define i1 @icmp_mul0_eq0(i32 %x) {
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%mul = mul i32 %x, 0
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%cmp = icmp eq i32 %mul, 0
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ret i1 %cmp
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}
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; CHECK: @icmp_mul0_ne0
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; CHECK-NEXT: ret i1 false
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define i1 @icmp_mul0_ne0(i32 %x) {
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%mul = mul i32 %x, 0
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%cmp = icmp ne i32 %mul, 0
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ret i1 %cmp
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}
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