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Renumber SSE execution domains for better code size.

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SSEDomainFix will collapse to the domain with the lower number when it has a
choice. The SSEPackedSingle domain often has smaller instructions, so prefer
that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99952 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2010-03-30 22:46:53 +00:00
parent 100f090add
commit 357be7f289
3 changed files with 21 additions and 24 deletions
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8
lib/Target/X86/X86InstrFormats.td
View File

@ -69,14 +69,14 @@ def CondMovFP : FPFormat<6>;
def SpecialFP : FPFormat<7>;
// Class specifying the SSE execution domain, used by the SSEDomainFix pass.
// Instruction execution domain.
// Keep in sync with tables in X86InstrInfo.cpp.
class Domain<bits<2> val> {
bits<2> Value = val;
}
def GenericDomain : Domain<0>;
def SSEPackedInt : Domain<1>;
def SSEPackedSingle : Domain<2>;
def SSEPackedDouble : Domain<3>;
def SSEPackedSingle : Domain<1>;
def SSEPackedDouble : Domain<2>;
def SSEPackedInt : Domain<3>;
// Prefix byte classes which are used to indicate to the ad-hoc machine code
// emitter that various prefix bytes are required.

32
lib/Target/X86/X86InstrInfo.cpp
View File

@ -3663,20 +3663,20 @@ unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
// by intrinsics.
static const unsigned ReplaceableInstrs[][3] = {
//PackedInt PackedSingle PackedDouble
{ X86::MOVDQAmr, X86::MOVAPSmr, X86::MOVAPDmr },
{ X86::MOVDQArm, X86::MOVAPSrm, X86::MOVAPDrm },
{ X86::MOVDQArr, X86::MOVAPSrr, X86::MOVAPDrr },
{ X86::MOVDQUmr, X86::MOVUPSmr, X86::MOVUPDmr },
{ X86::MOVDQUrm, X86::MOVUPSrm, X86::MOVUPDrm },
{ X86::MOVNTDQmr, X86::MOVNTPSmr, X86::MOVNTPDmr },
{ X86::PANDNrm, X86::ANDNPSrm, X86::ANDNPDrm },
{ X86::PANDNrr, X86::ANDNPSrr, X86::ANDNPDrr },
{ X86::PANDrm, X86::ANDPSrm, X86::ANDPDrm },
{ X86::PANDrr, X86::ANDPSrr, X86::ANDPDrr },
{ X86::PORrm, X86::ORPSrm, X86::ORPDrm },
{ X86::PORrr, X86::ORPSrr, X86::ORPDrr },
{ X86::PXORrm, X86::XORPSrm, X86::XORPDrm },
{ X86::PXORrr, X86::XORPSrr, X86::XORPDrr },
{ X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr },
{ X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm },
{ X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr },
{ X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr },
{ X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm },
{ X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr },
{ X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm },
{ X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr },
{ X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm },
{ X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr },
{ X86::ORPSrm, X86::ORPDrm, X86::PORrm },
{ X86::ORPSrr, X86::ORPDrr, X86::PORrr },
{ X86::XORPSrm, X86::XORPDrm, X86::PXORrm },
{ X86::XORPSrr, X86::XORPDrr, X86::PXORrr },
};
// FIXME: Some shuffle and unpack instructions have equivalents in different
@ -3692,8 +3692,8 @@ static const unsigned *lookup(unsigned opcode, unsigned domain) {
std::pair<uint16_t, uint16_t>
X86InstrInfo::GetSSEDomain(const MachineInstr *MI) const {
uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
return std::make_pair(domain, domain != NotSSEDomain &&
lookup(MI->getOpcode(), domain) ? 0xe : 0);
return std::make_pair(domain,
domain && lookup(MI->getOpcode(), domain) ? 0xe : 0);
}
void X86InstrInfo::SetSSEDomain(MachineInstr *MI, unsigned Domain) const {

5
lib/Target/X86/X86InstrInfo.h
View File

@ -399,7 +399,7 @@ namespace X86II {
GS = 2 << SegOvrShift,
// Execution domain for SSE instructions in bits 22, 23.
// 0 in bits 22-23 means normal, non-SSE instruction. See SSEDomain below.
// 0 in bits 22-23 means normal, non-SSE instruction.
SSEDomainShift = 22,
OpcodeShift = 24,
@ -719,9 +719,6 @@ public:
///
unsigned getGlobalBaseReg(MachineFunction *MF) const;
/// Some SSE instructions come in variants for three domains.
enum SSEDomain { NotSSEDomain, PackedInt, PackedSingle, PackedDouble };
/// GetSSEDomain - Return the SSE execution domain of MI as the first element,
/// and a bitmask of possible arguments to SetSSEDomain ase the second.
std::pair<uint16_t, uint16_t> GetSSEDomain(const MachineInstr *MI) const;