6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-09-30 19:55:11 +00:00
Code Issues Projects Releases Wiki Activity

Fix decoding of VMOVSRR and VMOVRRS, which account for the overwhelming majority of decoder crashes detected by randomized testing.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138269 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson 2011-08-22 20:27:12 +00:00
parent eeb37f1a56
commit 357ec6850b
3 changed files with 50 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
lib/Target/ARM/ARMInstrVFP.td
View File

@ -521,6 +521,7 @@ def VMOVRRS : AVConv3I<0b11000101, 0b1010,
// Some single precision VFP instructions may be executed on both NEON and VFP
// pipelines.
let D = VFPNeonDomain;
let DecoderMethod = "DecodeVMOVRRS";
}
} // neverHasSideEffects
@ -559,6 +560,8 @@ def VMOVSRR : AVConv5I<0b11000100, 0b1010,
// Some single precision VFP instructions may be executed on both NEON and VFP
// pipelines.
let D = VFPNeonDomain;
let DecoderMethod = "DecodeVMOVSRR";
}
// FMRDH: SPR -> GPR

45
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
View File

@ -175,6 +175,10 @@ static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
@ -3195,3 +3199,44 @@ static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
return S;
}
static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
DecodeStatus S = Success;
unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
CHECK(S, Unpredictable);
CHECK(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder));
CHECK(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder));
CHECK(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder));
CHECK(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder));
CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
return S;
}
static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
DecodeStatus S = Success;
unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
CHECK(S, Unpredictable);
CHECK(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder));
CHECK(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder));
CHECK(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder));
CHECK(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder));
CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
return S;
}

2
test/MC/Disassembler/ARM/neon.txt
View File

@ -1851,3 +1851,5 @@
0x0d 0x03 0x80 0xf4
# CHECK: vst4.8 {d0[0], d1[0], d2[0], d3[0]}, [r0]!
0x3d 0x2a 0x5e 0x6c
# CHECK: vmovvs r2, lr, s29, s30