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https://github.com/c64scene-ar/llvm-6502.git
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Fix some fast-isel problems selecting global variable addressing in
pic mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74582 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -457,20 +457,30 @@ bool X86FastISel::X86SelectAddress(Value *V, X86AddressMode &AM, bool isCall) {
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AM.GV = 0;
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return true;
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}
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// Issue load from stub if necessary.
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// Issue load from stub.
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unsigned Opc = 0;
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const TargetRegisterClass *RC = NULL;
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if (TLI.getPointerTy() == MVT::i32) {
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Opc = X86::MOV32rm;
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RC = X86::GR32RegisterClass;
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} else {
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Opc = X86::MOV64rm;
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RC = X86::GR64RegisterClass;
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}
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X86AddressMode StubAM;
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StubAM.Base.Reg = AM.Base.Reg;
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StubAM.GV = AM.GV;
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if (TLI.getPointerTy() == MVT::i32) {
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Opc = X86::MOV32rm;
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RC = X86::GR32RegisterClass;
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if (Subtarget->isPICStyleGOT() &&
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TM.getRelocationModel() == Reloc::PIC_)
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StubAM.GVOpFlags = X86II::MO_GOT;
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} else {
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Opc = X86::MOV64rm;
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RC = X86::GR64RegisterClass;
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if (TM.getRelocationModel() != Reloc::Static)
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StubAM.GVOpFlags = X86II::MO_GOTPCREL;
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}
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unsigned ResultReg = createResultReg(RC);
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addFullAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), StubAM);
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@ -49,8 +49,10 @@ struct X86AddressMode {
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unsigned IndexReg;
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unsigned Disp;
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GlobalValue *GV;
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unsigned GVOpFlags;
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X86AddressMode() : BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(0) {
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X86AddressMode()
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: BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(0), GVOpFlags(0) {
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Base.Reg = 0;
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}
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};
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@ -113,7 +115,7 @@ inline const MachineInstrBuilder &addLeaAddress(const MachineInstrBuilder &MIB,
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assert (0);
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MIB.addImm(AM.Scale).addReg(AM.IndexReg);
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if (AM.GV)
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return MIB.addGlobalAddress(AM.GV, AM.Disp);
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return MIB.addGlobalAddress(AM.GV, AM.Disp, AM.GVOpFlags);
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else
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return MIB.addImm(AM.Disp);
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}
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24
test/CodeGen/X86/fast-isel-gv.ll
Normal file
24
test/CodeGen/X86/fast-isel-gv.ll
Normal file
@ -0,0 +1,24 @@
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; RUN: llvm-as < %s | llc -fast-isel | grep {_kill@GOTPCREL}
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
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target triple = "x86_64-apple-darwin10.0"
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@f = global i8 (...)* @kill ; <i8 (...)**> [#uses=1]
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declare signext i8 @kill(...)
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define i32 @main() nounwind ssp {
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entry:
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%retval = alloca i32 ; <i32*> [#uses=2]
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%0 = alloca i32 ; <i32*> [#uses=2]
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%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
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%1 = load i8 (...)** @f, align 8 ; <i8 (...)*> [#uses=1]
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%2 = icmp ne i8 (...)* %1, @kill ; <i1> [#uses=1]
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%3 = zext i1 %2 to i32 ; <i32> [#uses=1]
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store i32 %3, i32* %0, align 4
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%4 = load i32* %0, align 4 ; <i32> [#uses=1]
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store i32 %4, i32* %retval, align 4
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br label %return
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return: ; preds = %entry
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%retval1 = load i32* %retval ; <i32> [#uses=1]
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ret i32 %retval1
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}
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