6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-08-05 13:26:55 +00:00
Code Issues Projects Releases Wiki Activity

change a ton of code to not implicitly use the "O" raw_ostream

Browse Source 
member of AsmPrinter.  Instead, pass it in explicitly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100306 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2010-04-04 04:47:45 +00:00
parent 20adc9dc46
commit 35c33bd772
25 changed files with 759 additions and 591 deletions
Download Patch File Download Diff File Expand all files Collapse all files

99
lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp
View File

@@ -52,33 +52,33 @@ namespace {
/// printInstruction - This method is automatically generated by tablegen
/// from the instruction set description.
void printInstruction(const MachineInstr *MI);
void printInstruction(const MachineInstr *MI, raw_ostream &OS);
static const char *getRegisterName(unsigned RegNo);
void EmitInstruction(const MachineInstr *MI) {
printInstruction(MI);
printInstruction(MI, O);
OutStreamer.AddBlankLine();
}
void printOp(const MachineOperand &MO);
void printOp(const MachineOperand &MO, raw_ostream &OS);
/// printRegister - Print register according to target requirements.
///
void printRegister(const MachineOperand &MO, bool R0AsZero) {
void printRegister(const MachineOperand &MO, bool R0AsZero, raw_ostream &O){
unsigned RegNo = MO.getReg();
assert(TargetRegisterInfo::isPhysicalRegister(RegNo) &&
"Not physreg??");
O << getRegisterName(RegNo);
}
void printOperand(const MachineInstr *MI, unsigned OpNo) {
void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) {
const MachineOperand &MO = MI->getOperand(OpNo);
if (MO.isReg()) {
O << getRegisterName(MO.getReg());
} else if (MO.isImm()) {
O << MO.getImm();
} else {
printOp(MO);
printOp(MO, O);
}
}
@@ -89,7 +89,7 @@ namespace {
void
printS7ImmOperand(const MachineInstr *MI, unsigned OpNo)
printS7ImmOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O)
{
int value = MI->getOperand(OpNo).getImm();
value = (value << (32 - 7)) >> (32 - 7);
@@ -100,7 +100,7 @@ namespace {
}
void
printU7ImmOperand(const MachineInstr *MI, unsigned OpNo)
printU7ImmOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O)
{
unsigned int value = MI->getOperand(OpNo).getImm();
assert(value < (1 << 8) && "Invalid u7 argument");
@@ -108,45 +108,45 @@ namespace {
}
void
printShufAddr(const MachineInstr *MI, unsigned OpNo)
printShufAddr(const MachineInstr *MI, unsigned OpNo, raw_ostream &O)
{
char value = MI->getOperand(OpNo).getImm();
O << (int) value;
O << "(";
printOperand(MI, OpNo+1);
printOperand(MI, OpNo+1, O);
O << ")";
}
void
printS16ImmOperand(const MachineInstr *MI, unsigned OpNo)
printS16ImmOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O)
{
O << (short) MI->getOperand(OpNo).getImm();
}
void
printU16ImmOperand(const MachineInstr *MI, unsigned OpNo)
printU16ImmOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O)
{
O << (unsigned short)MI->getOperand(OpNo).getImm();
}
void
printU32ImmOperand(const MachineInstr *MI, unsigned OpNo)
printU32ImmOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O)
{
O << (unsigned)MI->getOperand(OpNo).getImm();
}
void
printMemRegReg(const MachineInstr *MI, unsigned OpNo) {
printMemRegReg(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) {
// When used as the base register, r0 reads constant zero rather than
// the value contained in the register. For this reason, the darwin
// assembler requires that we print r0 as 0 (no r) when used as the base.
const MachineOperand &MO = MI->getOperand(OpNo);
O << getRegisterName(MO.getReg()) << ", ";
printOperand(MI, OpNo+1);
printOperand(MI, OpNo+1, O);
}
void
printU18ImmOperand(const MachineInstr *MI, unsigned OpNo)
printU18ImmOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O)
{
unsigned int value = MI->getOperand(OpNo).getImm();
assert(value <= (1 << 19) - 1 && "Invalid u18 argument");
@@ -154,7 +154,7 @@ namespace {
}
void
printS10ImmOperand(const MachineInstr *MI, unsigned OpNo)
printS10ImmOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O)
{
short value = (short) (((int) MI->getOperand(OpNo).getImm() << 16)
>> 16);
@@ -164,7 +164,7 @@ namespace {
}
void
printU10ImmOperand(const MachineInstr *MI, unsigned OpNo)
printU10ImmOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O)
{
short value = (short) (((int) MI->getOperand(OpNo).getImm() << 16)
>> 16);
@@ -173,7 +173,7 @@ namespace {
}
void
printDFormAddr(const MachineInstr *MI, unsigned OpNo)
printDFormAddr(const MachineInstr *MI, unsigned OpNo, raw_ostream &O)
{
assert(MI->getOperand(OpNo).isImm() &&
"printDFormAddr first operand is not immediate");
@@ -182,18 +182,18 @@ namespace {
assert((value16 >= -(1 << (9+4)) && value16 <= (1 << (9+4)) - 1)
&& "Invalid dform s10 offset argument");
O << (value16 & ~0xf) << "(";
printOperand(MI, OpNo+1);
printOperand(MI, OpNo+1, O);
O << ")";
}
void
printAddr256K(const MachineInstr *MI, unsigned OpNo)
printAddr256K(const MachineInstr *MI, unsigned OpNo, raw_ostream &O)
{
/* Note: operand 1 is an offset or symbol name. */
if (MI->getOperand(OpNo).isImm()) {
printS16ImmOperand(MI, OpNo);
printS16ImmOperand(MI, OpNo, O);
} else {
printOp(MI->getOperand(OpNo));
printOp(MI->getOperand(OpNo), O);
if (MI->getOperand(OpNo+1).isImm()) {
int displ = int(MI->getOperand(OpNo+1).getImm());
if (displ > 0)
@@ -204,50 +204,51 @@ namespace {
}
}
void printCallOperand(const MachineInstr *MI, unsigned OpNo) {
printOp(MI->getOperand(OpNo));
void printCallOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) {
printOp(MI->getOperand(OpNo), O);
}
void printPCRelativeOperand(const MachineInstr *MI, unsigned OpNo) {
void printPCRelativeOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) {
// Used to generate a ".-<target>", but it turns out that the assembler
// really wants the target.
//
// N.B.: This operand is used for call targets. Branch hints are another
// animal entirely.
printOp(MI->getOperand(OpNo));
printOp(MI->getOperand(OpNo), O);
}
void printHBROperand(const MachineInstr *MI, unsigned OpNo) {
void printHBROperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) {
// HBR operands are generated in front of branches, hence, the
// program counter plus the target.
O << ".+";
printOp(MI->getOperand(OpNo));
printOp(MI->getOperand(OpNo), O);
}
void printSymbolHi(const MachineInstr *MI, unsigned OpNo) {
void printSymbolHi(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) {
if (MI->getOperand(OpNo).isImm()) {
printS16ImmOperand(MI, OpNo);
printS16ImmOperand(MI, OpNo, O);
} else {
printOp(MI->getOperand(OpNo));
printOp(MI->getOperand(OpNo), O);
O << "@h";
}
}
void printSymbolLo(const MachineInstr *MI, unsigned OpNo) {
void printSymbolLo(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) {
if (MI->getOperand(OpNo).isImm()) {
printS16ImmOperand(MI, OpNo);
printS16ImmOperand(MI, OpNo, O);
} else {
printOp(MI->getOperand(OpNo));
printOp(MI->getOperand(OpNo), O);
O << "@l";
}
}
/// Print local store address
void printSymbolLSA(const MachineInstr *MI, unsigned OpNo) {
printOp(MI->getOperand(OpNo));
void printSymbolLSA(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) {
printOp(MI->getOperand(OpNo), O);
}
void printROTHNeg7Imm(const MachineInstr *MI, unsigned OpNo) {
void printROTHNeg7Imm(const MachineInstr *MI, unsigned OpNo,
raw_ostream &O) {
if (MI->getOperand(OpNo).isImm()) {
int value = (int) MI->getOperand(OpNo).getImm();
assert((value >= 0 && value < 16)
@@ -258,15 +259,13 @@ namespace {
}
}
void printROTNeg7Imm(const MachineInstr *MI, unsigned OpNo) {
if (MI->getOperand(OpNo).isImm()) {
int value = (int) MI->getOperand(OpNo).getImm();
assert((value >= 0 && value <= 32)
&& "Invalid negated immediate rotate 7-bit argument");
O << -value;
} else {
llvm_unreachable("Invalid/non-immediate rotate amount in printRotateNeg7Imm");
}
void printROTNeg7Imm(const MachineInstr *MI, unsigned OpNo, raw_ostream &O){
assert(MI->getOperand(OpNo).isImm() &&
"Invalid/non-immediate rotate amount in printRotateNeg7Imm");
int value = (int) MI->getOperand(OpNo).getImm();
assert((value >= 0 && value <= 32)
&& "Invalid negated immediate rotate 7-bit argument");
O << -value;
}
};
} // end of anonymous namespace
@@ -274,7 +273,7 @@ namespace {
// Include the auto-generated portion of the assembly writer
#include "SPUGenAsmWriter.inc"
void SPUAsmPrinter::printOp(const MachineOperand &MO) {
void SPUAsmPrinter::printOp(const MachineOperand &MO, raw_ostream &O) {
switch (MO.getType()) {
case MachineOperand::MO_Immediate:
llvm_report_error("printOp() does not handle immediate values");
@@ -341,7 +340,7 @@ bool SPUAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
}
}
printOperand(MI, OpNo);
printOperand(MI, OpNo, O);
return false;
}
@@ -351,7 +350,7 @@ bool SPUAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
const char *ExtraCode) {
if (ExtraCode && ExtraCode[0])
return true; // Unknown modifier.
printMemRegReg(MI, OpNo);
printMemRegReg(MI, OpNo, O);
return false;
}