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https://github.com/c64scene-ar/llvm-6502.git
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R600/SI: Reimplement isLegalAddressingMode
Now that we sometimes know the address space, this can theoretically do a better job. This needs better test coverage, but this mostly depends on first updating the loop optimizatiosn to provide the address space. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239053 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault
parent
013ef59713
commit
35cc03a1ea
@ -137,7 +137,10 @@ enum AddressSpaces {
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CONSTANT_BUFFER_14 = 22,
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CONSTANT_BUFFER_15 = 23,
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ADDRESS_NONE = 24, ///< Address space for unknown memory.
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LAST_ADDRESS = ADDRESS_NONE
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LAST_ADDRESS = ADDRESS_NONE,
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// Some places use this if the address space can't be determined.
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UNKNOWN_ADDRESS_SPACE = ~0u
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};
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} // namespace AMDGPUAS
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@ -250,47 +250,83 @@ bool SITargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &,
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return false;
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}
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// FIXME: This really needs an address space argument. The immediate offset
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// size is different for different sets of memory instruction sets.
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// The single offset DS instructions have a 16-bit unsigned byte offset.
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//
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// MUBUF / MTBUF have a 12-bit unsigned byte offset, and additionally can do r +
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// r + i with addr64. 32-bit has more addressing mode options. Depending on the
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// resource constant, it can also do (i64 r0) + (i32 r1) * (i14 i).
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//
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// SMRD instructions have an 8-bit, dword offset.
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//
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bool SITargetLowering::isLegalAddressingMode(const AddrMode &AM,
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Type *Ty, unsigned AS) const {
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// No global is ever allowed as a base.
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if (AM.BaseGV)
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return false;
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// Allow a 16-bit unsigned immediate field, since this is what DS instructions
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// use.
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if (!isUInt<16>(AM.BaseOffs))
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return false;
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switch (AS) {
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case AMDGPUAS::GLOBAL_ADDRESS:
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case AMDGPUAS::CONSTANT_ADDRESS: // XXX - Should we assume SMRD instructions?
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case AMDGPUAS::PRIVATE_ADDRESS:
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case AMDGPUAS::UNKNOWN_ADDRESS_SPACE: {
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// MUBUF / MTBUF instructions have a 12-bit unsigned byte offset, and
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// additionally can do r + r + i with addr64. 32-bit has more addressing
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// mode options. Depending on the resource constant, it can also do
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// (i64 r0) + (i32 r1) * (i14 i).
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//
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// SMRD instructions have an 8-bit, dword offset.
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//
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// Assume nonunifom access, since the address space isn't enough to know
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// what instruction we will use, and since we don't know if this is a load
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// or store and scalar stores are only available on VI.
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//
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// We also know if we are doing an extload, we can't do a scalar load.
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//
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// Private arrays end up using a scratch buffer most of the time, so also
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// assume those use MUBUF instructions. Scratch loads / stores are currently
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// implemented as mubuf instructions with offen bit set, so slightly
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// different than the normal addr64.
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if (!isUInt<12>(AM.BaseOffs))
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return false;
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// Only support r+r,
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switch (AM.Scale) {
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case 0: // "r+i" or just "i", depending on HasBaseReg.
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break;
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case 1:
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if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
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// FIXME: Since we can split immediate into soffset and immediate offset,
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// would it make sense to allow any immediate?
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switch (AM.Scale) {
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case 0: // r + i or just i, depending on HasBaseReg.
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return true;
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case 1:
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return true; // We have r + r or r + i.
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case 2:
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if (AM.HasBaseReg) {
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// Reject 2 * r + r.
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return false;
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}
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// Allow 2 * r as r + r
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// Or 2 * r + i is allowed as r + r + i.
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return true;
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default: // Don't allow n * r
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return false;
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// Otherwise we have r+r or r+i.
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break;
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case 2:
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if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
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}
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}
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case AMDGPUAS::LOCAL_ADDRESS:
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case AMDGPUAS::REGION_ADDRESS: {
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// Basic, single offset DS instructions allow a 16-bit unsigned immediate
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// field.
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// XXX - If doing a 4-byte aligned 8-byte type access, we effectively have
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// an 8-bit dword offset but we don't know the alignment here.
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if (!isUInt<16>(AM.BaseOffs))
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return false;
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// Allow 2*r as r+r.
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break;
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default: // Don't allow n * r
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if (AM.Scale == 0) // r + i or just i, depending on HasBaseReg.
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return true;
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if (AM.Scale == 1 && AM.HasBaseReg)
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return true;
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return false;
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}
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return true;
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case AMDGPUAS::FLAT_ADDRESS: {
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// Flat instructions do not have offsets, and only have the register
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// address.
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return AM.BaseOffs == 0 && (AM.Scale == 0 || AM.Scale == 1);
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}
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default:
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llvm_unreachable("unhandled address space");
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}
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}
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bool SITargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
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242
test/CodeGen/R600/cgp-addressing-modes.ll
Normal file
242
test/CodeGen/R600/cgp-addressing-modes.ll
Normal file
@ -0,0 +1,242 @@
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; RUN: opt -S -codegenprepare -mtriple=amdgcn-unknown-unknown < %s | FileCheck -check-prefix=OPT %s
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; RUN: llc -march=amdgcn -mattr=-promote-alloca < %s | FileCheck -check-prefix=GCN %s
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declare i32 @llvm.r600.read.tidig.x() #0
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; OPT-LABEL: @test_sink_global_small_offset_i32(
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; OPT-NOT: getelementptr i32, i32 addrspace(1)* %in
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; OPT: br i1
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; OPT: ptrtoint
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; GCN-LABEL: {{^}}test_sink_global_small_offset_i32:
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; GCN: {{^}}BB0_2:
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define void @test_sink_global_small_offset_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %cond) {
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entry:
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%out.gep = getelementptr i32, i32 addrspace(1)* %out, i64 999999
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%in.gep = getelementptr i32, i32 addrspace(1)* %in, i64 7
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%tmp0 = icmp eq i32 %cond, 0
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br i1 %tmp0, label %endif, label %if
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if:
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%tmp1 = load i32, i32 addrspace(1)* %in.gep
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br label %endif
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endif:
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%x = phi i32 [ %tmp1, %if ], [ 0, %entry ]
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store i32 %x, i32 addrspace(1)* %out.gep
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br label %done
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done:
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ret void
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}
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; OPT-LABEL: @test_sink_global_small_max_i32_ds_offset(
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; OPT: %in.gep = getelementptr i8, i8 addrspace(1)* %in, i64 65535
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; OPT: br i1
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; GCN-LABEL: {{^}}test_sink_global_small_max_i32_ds_offset:
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; GCN: s_and_saveexec_b64
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; GCN: buffer_load_sbyte {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, s{{[0-9]+$}}
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; GCN: {{^}}BB1_2:
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; GCN: s_or_b64 exec
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define void @test_sink_global_small_max_i32_ds_offset(i32 addrspace(1)* %out, i8 addrspace(1)* %in, i32 %cond) {
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entry:
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%out.gep = getelementptr i32, i32 addrspace(1)* %out, i64 99999
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%in.gep = getelementptr i8, i8 addrspace(1)* %in, i64 65535
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%tmp0 = icmp eq i32 %cond, 0
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br i1 %tmp0, label %endif, label %if
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if:
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%tmp1 = load i8, i8 addrspace(1)* %in.gep
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%tmp2 = sext i8 %tmp1 to i32
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br label %endif
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endif:
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%x = phi i32 [ %tmp2, %if ], [ 0, %entry ]
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store i32 %x, i32 addrspace(1)* %out.gep
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br label %done
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done:
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ret void
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}
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; GCN-LABEL: {{^}}test_sink_global_small_max_mubuf_offset:
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; GCN: s_and_saveexec_b64
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; GCN: buffer_load_sbyte {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:4095{{$}}
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; GCN: {{^}}BB2_2:
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; GCN: s_or_b64 exec
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define void @test_sink_global_small_max_mubuf_offset(i32 addrspace(1)* %out, i8 addrspace(1)* %in, i32 %cond) {
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entry:
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%out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 1024
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%in.gep = getelementptr i8, i8 addrspace(1)* %in, i64 4095
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%tmp0 = icmp eq i32 %cond, 0
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br i1 %tmp0, label %endif, label %if
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if:
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%tmp1 = load i8, i8 addrspace(1)* %in.gep
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%tmp2 = sext i8 %tmp1 to i32
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br label %endif
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endif:
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%x = phi i32 [ %tmp2, %if ], [ 0, %entry ]
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store i32 %x, i32 addrspace(1)* %out.gep
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br label %done
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done:
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ret void
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}
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; GCN-LABEL: {{^}}test_sink_global_small_max_plus_1_mubuf_offset:
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; GCN: s_and_saveexec_b64
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; GCN: buffer_load_sbyte {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, s{{[0-9]+$}}
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; GCN: {{^}}BB3_2:
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; GCN: s_or_b64 exec
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define void @test_sink_global_small_max_plus_1_mubuf_offset(i32 addrspace(1)* %out, i8 addrspace(1)* %in, i32 %cond) {
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entry:
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%out.gep = getelementptr i32, i32 addrspace(1)* %out, i64 99999
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%in.gep = getelementptr i8, i8 addrspace(1)* %in, i64 4096
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%tmp0 = icmp eq i32 %cond, 0
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br i1 %tmp0, label %endif, label %if
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if:
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%tmp1 = load i8, i8 addrspace(1)* %in.gep
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%tmp2 = sext i8 %tmp1 to i32
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br label %endif
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endif:
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%x = phi i32 [ %tmp2, %if ], [ 0, %entry ]
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store i32 %x, i32 addrspace(1)* %out.gep
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br label %done
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done:
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ret void
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}
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; OPT-LABEL: @test_no_sink_flat_small_offset_i32(
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; OPT: getelementptr i32, i32 addrspace(4)* %in
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; OPT: br i1
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; OPT-NOT: ptrtoint
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; GCN-LABEL: {{^}}test_no_sink_flat_small_offset_i32:
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; GCN: flat_load_dword
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; GCN: {{^}}BB4_2:
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define void @test_no_sink_flat_small_offset_i32(i32 addrspace(4)* %out, i32 addrspace(4)* %in, i32 %cond) {
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entry:
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%out.gep = getelementptr i32, i32 addrspace(4)* %out, i64 999999
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%in.gep = getelementptr i32, i32 addrspace(4)* %in, i64 7
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%tmp0 = icmp eq i32 %cond, 0
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br i1 %tmp0, label %endif, label %if
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if:
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%tmp1 = load i32, i32 addrspace(4)* %in.gep
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br label %endif
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endif:
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%x = phi i32 [ %tmp1, %if ], [ 0, %entry ]
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store i32 %x, i32 addrspace(4)* %out.gep
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br label %done
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done:
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ret void
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}
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; OPT-LABEL: @test_sink_scratch_small_offset_i32(
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; OPT-NOT: getelementptr [512 x i32]
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; OPT: br i1
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; OPT: ptrtoint
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; GCN-LABEL: {{^}}test_sink_scratch_small_offset_i32:
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; GCN: s_and_saveexec_b64
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; GCN: buffer_store_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen offset:4092{{$}}
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; GCN: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen offset:4092{{$}}
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; GCN: {{^}}BB5_2:
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define void @test_sink_scratch_small_offset_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %cond, i32 %arg) {
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entry:
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%alloca = alloca [512 x i32], align 4
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%out.gep.0 = getelementptr i32, i32 addrspace(1)* %out, i64 999998
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%out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i64 999999
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%add.arg = add i32 %arg, 8
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%alloca.gep = getelementptr [512 x i32], [512 x i32]* %alloca, i32 0, i32 1023
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%tmp0 = icmp eq i32 %cond, 0
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br i1 %tmp0, label %endif, label %if
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if:
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store volatile i32 123, i32* %alloca.gep
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%tmp1 = load volatile i32, i32* %alloca.gep
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br label %endif
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endif:
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%x = phi i32 [ %tmp1, %if ], [ 0, %entry ]
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store i32 %x, i32 addrspace(1)* %out.gep.0
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%load = load volatile i32, i32* %alloca.gep
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store i32 %load, i32 addrspace(1)* %out.gep.1
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br label %done
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done:
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ret void
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}
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; OPT-LABEL: @test_no_sink_scratch_large_offset_i32(
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; OPT: %alloca.gep = getelementptr [512 x i32], [512 x i32]* %alloca, i32 0, i32 1024
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; OPT: br i1
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; OPT-NOT: ptrtoint
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; GCN-LABEL: {{^}}test_no_sink_scratch_large_offset_i32:
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; GCN: s_and_saveexec_b64
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; GCN: buffer_store_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen{{$}}
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; GCN: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen{{$}}
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; GCN: {{^}}BB6_2:
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define void @test_no_sink_scratch_large_offset_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %cond, i32 %arg) {
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entry:
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%alloca = alloca [512 x i32], align 4
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%out.gep.0 = getelementptr i32, i32 addrspace(1)* %out, i64 999998
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%out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i64 999999
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%add.arg = add i32 %arg, 8
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%alloca.gep = getelementptr [512 x i32], [512 x i32]* %alloca, i32 0, i32 1024
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%tmp0 = icmp eq i32 %cond, 0
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br i1 %tmp0, label %endif, label %if
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if:
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store volatile i32 123, i32* %alloca.gep
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%tmp1 = load volatile i32, i32* %alloca.gep
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br label %endif
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endif:
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%x = phi i32 [ %tmp1, %if ], [ 0, %entry ]
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store i32 %x, i32 addrspace(1)* %out.gep.0
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%load = load volatile i32, i32* %alloca.gep
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store i32 %load, i32 addrspace(1)* %out.gep.1
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br label %done
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done:
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ret void
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}
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; GCN-LABEL: {{^}}test_sink_global_vreg_sreg_i32:
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; GCN: s_and_saveexec_b64
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; GCN: buffer_load_dword {{v[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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; GCN: {{^}}BB7_2:
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define void @test_sink_global_vreg_sreg_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %offset, i32 %cond) {
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entry:
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%offset.ext = zext i32 %offset to i64
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%out.gep = getelementptr i32, i32 addrspace(1)* %out, i64 999999
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%in.gep = getelementptr i32, i32 addrspace(1)* %in, i64 %offset.ext
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%tmp0 = icmp eq i32 %cond, 0
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br i1 %tmp0, label %endif, label %if
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if:
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%tmp1 = load i32, i32 addrspace(1)* %in.gep
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br label %endif
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endif:
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%x = phi i32 [ %tmp1, %if ], [ 0, %entry ]
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store i32 %x, i32 addrspace(1)* %out.gep
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br label %done
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done:
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ret void
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}
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind }
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