diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td
index ce39a3f7376..2d76a3615f6 100644
--- a/lib/Target/ARM/ARMInstrFormats.td
+++ b/lib/Target/ARM/ARMInstrFormats.td
@@ -808,6 +808,10 @@ class ThumbI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
 class TI<dag oops, dag iops, string asm, list<dag> pattern>
   : ThumbI<oops, iops, AddrModeNone, Size2Bytes, asm, "", pattern>;
 
+// Two-address instructions
+class TIt<dag oops, dag iops, string asm, list<dag> pattern>
+  : ThumbI<oops, iops, AddrModeNone, Size2Bytes, asm, "$lhs = $dst", pattern>;
+
 // tBL, tBX instructions
 class TIx2<dag oops, dag iops, string asm, list<dag> pattern>
   : ThumbI<oops, iops, AddrModeNone, Size4Bytes, asm, "", pattern>;
diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td
index 9917e016dd0..cc4f20c682c 100644
--- a/lib/Target/ARM/ARMInstrThumb.td
+++ b/lib/Target/ARM/ARMInstrThumb.td
@@ -127,10 +127,11 @@ PseudoInst<(outs), (ins i32imm:$amt),
            [(ARMcallseq_start imm:$amt)]>, Requires<[IsThumb1Only]>;
 }
 
+// For both thumb1 and thumb2.
 let isNotDuplicable = 1 in
-def tPICADD : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, pclabel:$cp),
-                  "$cp:\n\tadd $dst, pc",
-                  [(set tGPR:$dst, (ARMpic_add tGPR:$lhs, imm:$cp))]>;
+def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp),
+                 "$cp:\n\tadd $dst, pc",
+                 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>;
 
 // PC relative add.
 def tADDrPCi : T1I<(outs tGPR:$dst), (ins i32imm:$rhs),
diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td
index faa7dd5475d..1b6b575a9ac 100644
--- a/lib/Target/ARM/ARMInstrThumb2.td
+++ b/lib/Target/ARM/ARMInstrThumb2.td
@@ -422,12 +422,6 @@ multiclass T2I_bin_rrot<string opc, PatFrag opnode> {
 //  Miscellaneous Instructions.
 //
 
-let isNotDuplicable = 1 in
-def t2PICADD : T2XI<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp),
-                    "$cp:\n\tadd.w $dst, $lhs, pc",
-                    [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>;
-
-
 // LEApcrel - Load a pc-relative address into a register without offending the
 // assembler.
 def t2LEApcrel : T2XI<(outs GPR:$dst), (ins i32imm:$label, pred:$p),
diff --git a/test/CodeGen/Thumb2/load-global.ll b/test/CodeGen/Thumb2/load-global.ll
index 24aaf21f498..4aad567fa8f 100644
--- a/test/CodeGen/Thumb2/load-global.ll
+++ b/test/CodeGen/Thumb2/load-global.ll
@@ -17,7 +17,7 @@ define i32 @test1() {
 ; DYNAMIC: .long L_G$non_lazy_ptr
 
 ; PIC: _test1
-; PIC: add.w r0, r0, pc
+; PIC: add r0, pc
 ; PIC: .long L_G$non_lazy_ptr-(LPC0+4)
 
 ; LINUX: test1
diff --git a/test/CodeGen/Thumb2/pic-load.ll b/test/CodeGen/Thumb2/pic-load.ll
index 553377b48bc..92862c87e7a 100644
--- a/test/CodeGen/Thumb2/pic-load.ll
+++ b/test/CodeGen/Thumb2/pic-load.ll
@@ -8,7 +8,7 @@
 define hidden arm_apcscc i32 @atexit(void ()* %func) nounwind {
 entry:
 ; CHECK: atexit:
-; CHECK: add.w r0, r0, pc
+; CHECK: add r0, pc
 	%r = alloca %struct.one_atexit_routine, align 4		; <%struct.one_atexit_routine*> [#uses=3]
 	%0 = getelementptr %struct.one_atexit_routine* %r, i32 0, i32 0, i32 0		; <void ()**> [#uses=1]
 	store void ()* %func, void ()** %0, align 4