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Rename Pair to RCPair lacking any better naming ideas.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134210 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -7528,8 +7528,8 @@ ARMTargetLowering::getSingleConstraintMatchWeight(
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return weight;
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}
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typedef std::pair<unsigned, const TargetRegisterClass*> Pair;
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Pair
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typedef std::pair<unsigned, const TargetRegisterClass*> RCPair;
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RCPair
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ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
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EVT VT) const {
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if (Constraint.size() == 1) {
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@ -7537,23 +7537,23 @@ ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
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switch (Constraint[0]) {
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case 'l': // Low regs or general regs.
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if (Subtarget->isThumb())
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return Pair(0U, ARM::tGPRRegisterClass);
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return RCPair(0U, ARM::tGPRRegisterClass);
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else
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return Pair(0U, ARM::GPRRegisterClass);
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return RCPair(0U, ARM::GPRRegisterClass);
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case 'h': // High regs or no regs.
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if (Subtarget->isThumb())
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return Pair(0U, ARM::hGPRRegisterClass);
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return RCPair(0U, ARM::hGPRRegisterClass);
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else
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return Pair(0u, static_cast<const TargetRegisterClass*>(0));
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return RCPair(0u, static_cast<const TargetRegisterClass*>(0));
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case 'r':
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return Pair(0U, ARM::GPRRegisterClass);
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return RCPair(0U, ARM::GPRRegisterClass);
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case 'w':
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if (VT == MVT::f32)
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return Pair(0U, ARM::SPRRegisterClass);
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return RCPair(0U, ARM::SPRRegisterClass);
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if (VT.getSizeInBits() == 64)
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return Pair(0U, ARM::DPRRegisterClass);
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return RCPair(0U, ARM::DPRRegisterClass);
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if (VT.getSizeInBits() == 128)
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return Pair(0U, ARM::QPRRegisterClass);
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return RCPair(0U, ARM::QPRRegisterClass);
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break;
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}
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}
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