Added support for disassembling unpredictable swp/swpb ARM instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155004 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Silviu Baranga 2012-04-18 14:18:57 +00:00
parent 6b9f97dd89
commit 35ee7d28a6
4 changed files with 33 additions and 2 deletions

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@ -532,6 +532,7 @@ class AIswp<bit b, dag oops, dag iops, string opc, list<dag> pattern>
let Inst{11-4} = 0b00001001;
let Inst{3-0} = Rt2;
let Unpredictable{11-8} = 0b1111;
let DecoderMethod = "DecodeSwap";
}

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@ -4280,9 +4280,9 @@ def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", []>,
// SWP/SWPB are deprecated in V6/V7.
let mayLoad = 1, mayStore = 1 in {
def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, addr_offset_none:$addr),
def SWP : AIswp<0, (outs GPRnopc:$Rt), (ins GPRnopc:$Rt2, addr_offset_none:$addr),
"swp", []>;
def SWPB: AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, addr_offset_none:$addr),
def SWPB: AIswp<1, (outs GPRnopc:$Rt), (ins GPRnopc:$Rt2, addr_offset_none:$addr),
"swpb", []>;
}

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@ -4310,6 +4310,10 @@ static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
DecodeStatus S = MCDisassembler::Success;
if (Rt == Rn || Rn == Rt2)
S = MCDisassembler::SoftFail;
if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
return MCDisassembler::Fail;
if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))

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@ -0,0 +1,26 @@
# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s
# CHECK: potentially undefined
# CHECK: 0x9f 0x10 0x03 0x01
0x9f 0x10 0x03 0x01
# CHECK: potentially undefined
# CHECK: 0x90 0xf0 0x03 0x01
0x90 0xf0 0x03 0x01
# CHECK: potentially undefined
# CHECK: 0x90 0x1f 0x03 0x01
0x90 0x1f 0x03 0x01
# CHECK: potentially undefined
# CHECK: 0x90 0x10 0x0f 0x01
0x90 0x10 0x0f 0x01
# CHECK: potentially undefined
# CHECK: 0x90 0x10 0x01 0x01
0x90 0x10 0x01 0x01
# CHECK: potentially undefined
# CHECK: 0x90 0x10 0x00 0x01
0x90 0x10 0x00 0x01