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Add bulk of returning of values to Mips fast-isel
Summary: Implement the bulk of returning values in Mips fast-isel Test Plan: reatabi.ll Passes test-suite at -O0,-O2 and with mips32r2 and mips32r1. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits, aemerson, rfuhler Differential Revision: http://reviews.llvm.org/D5920 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228958 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Reed Kotler
parent
53a7b568b2
commit
36068aae42
@ -1,7 +1,6 @@
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//===-- MipsastISel.cpp - Mips FastISel implementation
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//---------------------===//
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#include "llvm/CodeGen/FunctionLoweringInfo.h"
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#include "MipsCCState.h"
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#include "MipsISelLowering.h"
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#include "MipsMachineFunction.h"
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@ -10,7 +9,9 @@
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#include "MipsTargetMachine.h"
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#include "llvm/Analysis/TargetLibraryInfo.h"
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#include "llvm/CodeGen/FastISel.h"
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#include "llvm/CodeGen/FunctionLoweringInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/GlobalAlias.h"
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#include "llvm/IR/GlobalVariable.h"
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#include "llvm/Target/TargetInstrInfo.h"
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@ -984,14 +985,88 @@ bool MipsFastISel::fastLowerCall(CallLoweringInfo &CLI) {
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}
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bool MipsFastISel::selectRet(const Instruction *I) {
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const Function &F = *I->getParent()->getParent();
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const ReturnInst *Ret = cast<ReturnInst>(I);
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if (!FuncInfo.CanLowerReturn)
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return false;
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// Build a list of return value registers.
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SmallVector<unsigned, 4> RetRegs;
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if (Ret->getNumOperands() > 0) {
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return false;
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CallingConv::ID CC = F.getCallingConv();
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SmallVector<ISD::OutputArg, 4> Outs;
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GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI);
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// Analyze operands of the call, assigning locations to each operand.
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SmallVector<CCValAssign, 16> ValLocs;
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MipsCCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs,
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I->getContext());
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CCAssignFn *RetCC = RetCC_Mips;
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CCInfo.AnalyzeReturn(Outs, RetCC);
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// Only handle a single return value for now.
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if (ValLocs.size() != 1)
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return false;
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CCValAssign &VA = ValLocs[0];
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const Value *RV = Ret->getOperand(0);
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// Don't bother handling odd stuff for now.
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if ((VA.getLocInfo() != CCValAssign::Full) &&
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(VA.getLocInfo() != CCValAssign::BCvt))
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return false;
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// Only handle register returns for now.
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if (!VA.isRegLoc())
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return false;
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unsigned Reg = getRegForValue(RV);
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if (Reg == 0)
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return false;
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unsigned SrcReg = Reg + VA.getValNo();
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unsigned DestReg = VA.getLocReg();
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// Avoid a cross-class copy. This is very unlikely.
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if (!MRI.getRegClass(SrcReg)->contains(DestReg))
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return false;
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EVT RVEVT = TLI.getValueType(RV->getType());
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if (!RVEVT.isSimple())
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return false;
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if (RVEVT.isVector())
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return false;
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MVT RVVT = RVEVT.getSimpleVT();
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if (RVVT == MVT::f128)
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return false;
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MVT DestVT = VA.getValVT();
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// Special handling for extended integers.
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if (RVVT != DestVT) {
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if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
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return false;
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if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt())
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return false;
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bool IsZExt = Outs[0].Flags.isZExt();
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SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt);
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if (SrcReg == 0)
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return false;
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}
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// Make the copy.
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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TII.get(TargetOpcode::COPY), DestReg).addReg(SrcReg);
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// Add register to return instruction.
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RetRegs.push_back(VA.getLocReg());
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}
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emitInst(Mips::RetRA);
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MachineInstrBuilder MIB = emitInst(Mips::RetRA);
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for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
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MIB.addReg(RetRegs[i], RegState::Implicit);
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return true;
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}
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@ -1116,7 +1191,8 @@ bool MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
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unsigned MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
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bool isZExt) {
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unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
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return emitIntExt(SrcVT, SrcReg, DestVT, DestReg, isZExt);
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bool Success = emitIntExt(SrcVT, SrcReg, DestVT, DestReg, isZExt);
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return Success ? DestReg : 0;
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}
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bool MipsFastISel::fastSelectInstruction(const Instruction *I) {
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80
test/CodeGen/Mips/Fast-ISel/retabi.ll
Normal file
80
test/CodeGen/Mips/Fast-ISel/retabi.ll
Normal file
@ -0,0 +1,80 @@
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; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
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; RUN: < %s | FileCheck %s
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@i = global i32 75, align 4
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@s = global i16 -345, align 2
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@c = global i8 118, align 1
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@f = global float 0x40BE623360000000, align 4
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@d = global double 1.298330e+03, align 8
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; Function Attrs: nounwind
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define i32 @reti() {
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entry:
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; CHECK-LABEL: reti:
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%0 = load i32* @i, align 4
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ret i32 %0
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; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
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; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
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; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
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; CHECK: lw $[[REG_I_ADDR:[0-9]+]], %got(i)($[[REG_GP]])
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; CHECK: lw $2, 0($[[REG_I_ADDR]])
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; CHECK: jr $ra
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}
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; Function Attrs: nounwind
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define signext i16 @rets() {
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entry:
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; CHECK-LABEL: rets:
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%0 = load i16* @s, align 2
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ret i16 %0
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; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
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; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
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; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
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; CHECK: lw $[[REG_S_ADDR:[0-9]+]], %got(s)($[[REG_GP]])
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; CHECK: lhu $[[REG_S:[0-9]+]], 0($[[REG_S_ADDR]])
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; CHECK: seh $2, $[[REG_S]]
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; CHECK: jr $ra
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}
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; Function Attrs: nounwind
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define signext i8 @retc() {
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entry:
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; CHECK-LABEL: retc:
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%0 = load i8* @c, align 1
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ret i8 %0
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; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
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; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
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; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
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; CHECK: lw $[[REG_C_ADDR:[0-9]+]], %got(c)($[[REG_GP]])
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; CHECK: lbu $[[REG_C:[0-9]+]], 0($[[REG_C_ADDR]])
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; CHECK: seb $2, $[[REG_C]]
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; CHECK: jr $ra
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}
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; Function Attrs: nounwind
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define float @retf() {
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entry:
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; CHECK-LABEL: retf:
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%0 = load float* @f, align 4
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ret float %0
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; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
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; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
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; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
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; CHECK: lw $[[REG_F_ADDR:[0-9]+]], %got(f)($[[REG_GP]])
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; CHECK: lwc1 $f0, 0($[[REG_F_ADDR]])
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; CHECK: jr $ra
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}
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; Function Attrs: nounwind
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define double @retd() {
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entry:
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; CHECK-LABEL: retd:
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%0 = load double* @d, align 8
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ret double %0
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; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
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; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
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; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
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; CHECK: lw $[[REG_D_ADDR:[0-9]+]], %got(d)($[[REG_GP]])
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; CHECK: ldc1 $f0, 0($[[REG_D_ADDR]])
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; CHECK: jr $ra
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}
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