diff --git a/lib/CodeGen/RegAllocSimple.cpp b/lib/CodeGen/RegAllocSimple.cpp index ad09f8220f8..0a911249618 100644 --- a/lib/CodeGen/RegAllocSimple.cpp +++ b/lib/CodeGen/RegAllocSimple.cpp @@ -199,17 +199,20 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) { unsigned physReg = Virt2PhysRegMap[virtualReg]; if (physReg == 0) { if (op.isDef()) { - if (!TM->getInstrInfo()->isTwoAddrInstr(MI->getOpcode()) || i) { + int TiedOp = TM->getInstrInfo() + ->getTiedToSrcOperand(MI->getOpcode(), i); + if (TiedOp == -1) { physReg = getFreeReg(virtualReg); } else { - // must be same register number as the first operand - // This maps a = b + c into b = b + c, and saves b into a's spot. - assert(MI->getOperand(1).isRegister() && - MI->getOperand(1).getReg() && - MI->getOperand(1).isUse() && + // must be same register number as the source operand that is + // tied to. This maps a = b + c into b = b + c, and saves b into + // a's spot. + assert(MI->getOperand(TiedOp).isRegister() && + MI->getOperand(TiedOp).getReg() && + MI->getOperand(TiedOp).isUse() && "Two address instruction invalid!"); - physReg = MI->getOperand(1).getReg(); + physReg = MI->getOperand(TiedOp).getReg(); } spillVirtReg(MBB, next(MI), virtualReg, physReg); } else { diff --git a/lib/CodeGen/TwoAddressInstructionPass.cpp b/lib/CodeGen/TwoAddressInstructionPass.cpp index 7db9958bc00..50599c850de 100644 --- a/lib/CodeGen/TwoAddressInstructionPass.cpp +++ b/lib/CodeGen/TwoAddressInstructionPass.cpp @@ -95,122 +95,141 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) { mi != me; ++mi) { unsigned opcode = mi->getOpcode(); - // ignore if it is not a two-address instruction - if (!TII.isTwoAddrInstr(opcode)) - continue; + bool FirstTied = true; + for (unsigned si = 1, e = TII.getNumOperands(opcode); si < e; ++si) { + int ti = TII.getOperandConstraint(opcode, si, TargetInstrInfo::TIED_TO); + if (ti == -1) + continue; - ++NumTwoAddressInstrs; - DEBUG(std::cerr << '\t'; mi->print(std::cerr, &TM)); - assert(mi->getOperand(1).isRegister() && mi->getOperand(1).getReg() && - mi->getOperand(1).isUse() && "two address instruction invalid"); + if (FirstTied) { + ++NumTwoAddressInstrs; + DEBUG(std::cerr << '\t'; mi->print(std::cerr, &TM)); + } + FirstTied = false; - // if the two operands are the same we just remove the use - // and mark the def as def&use, otherwise we have to insert a copy. - if (mi->getOperand(0).getReg() != mi->getOperand(1).getReg()) { - // rewrite: - // a = b op c - // to: - // a = b - // a = a op c - unsigned regA = mi->getOperand(0).getReg(); - unsigned regB = mi->getOperand(1).getReg(); + assert(mi->getOperand(si).isRegister() && mi->getOperand(si).getReg() && + mi->getOperand(si).isUse() && "two address instruction invalid"); - assert(MRegisterInfo::isVirtualRegister(regA) && - MRegisterInfo::isVirtualRegister(regB) && - "cannot update physical register live information"); + // if the two operands are the same we just remove the use + // and mark the def as def&use, otherwise we have to insert a copy. + if (mi->getOperand(ti).getReg() != mi->getOperand(si).getReg()) { + // rewrite: + // a = b op c + // to: + // a = b + // a = a op c + unsigned regA = mi->getOperand(ti).getReg(); + unsigned regB = mi->getOperand(si).getReg(); + + assert(MRegisterInfo::isVirtualRegister(regA) && + MRegisterInfo::isVirtualRegister(regB) && + "cannot update physical register live information"); #ifndef NDEBUG - // First, verify that we do not have a use of a in the instruction (a = - // b + a for example) because our transformation will not work. This - // should never occur because we are in SSA form. - for (unsigned i = 1; i != mi->getNumOperands(); ++i) - assert(!mi->getOperand(i).isRegister() || - mi->getOperand(i).getReg() != regA); + // First, verify that we don't have a use of a in the instruction (a = + // b + a for example) because our transformation will not work. This + // should never occur because we are in SSA form. + for (unsigned i = 0; i != mi->getNumOperands(); ++i) + assert((int)i == ti || + !mi->getOperand(i).isRegister() || + mi->getOperand(i).getReg() != regA); #endif - // If this instruction is not the killing user of B, see if we can - // rearrange the code to make it so. Making it the killing user will - // allow us to coalesce A and B together, eliminating the copy we are - // about to insert. - if (!LV.KillsRegister(mi, regB)) { - const TargetInstrDescriptor &TID = TII.get(opcode); + // If this instruction is not the killing user of B, see if we can + // rearrange the code to make it so. Making it the killing user will + // allow us to coalesce A and B together, eliminating the copy we are + // about to insert. + if (!LV.KillsRegister(mi, regB)) { + const TargetInstrDescriptor &TID = TII.get(opcode); - // If this instruction is commutative, check to see if C dies. If so, - // swap the B and C operands. This makes the live ranges of A and C - // joinable. - if (TID.Flags & M_COMMUTABLE) { - assert(mi->getOperand(2).isRegister() && - "Not a proper commutative instruction!"); - unsigned regC = mi->getOperand(2).getReg(); - if (LV.KillsRegister(mi, regC)) { - DEBUG(std::cerr << "2addr: COMMUTING : " << *mi); - MachineInstr *NewMI = TII.commuteInstruction(mi); - if (NewMI == 0) { - DEBUG(std::cerr << "2addr: COMMUTING FAILED!\n"); - } else { - DEBUG(std::cerr << "2addr: COMMUTED TO: " << *NewMI); - // If the instruction changed to commute it, update livevar. - if (NewMI != mi) { - LV.instructionChanged(mi, NewMI); // Update live variables - mbbi->insert(mi, NewMI); // Insert the new inst - mbbi->erase(mi); // Nuke the old inst. - mi = NewMI; + // If this instruction is commutative, check to see if C dies. If + // so, swap the B and C operands. This makes the live ranges of A + // and C joinable. + // FIXME: This code also works for A := B op C instructions. + if ((TID.Flags & M_COMMUTABLE) && mi->getNumOperands() == 3) { + assert(mi->getOperand(3-si).isRegister() && + "Not a proper commutative instruction!"); + unsigned regC = mi->getOperand(3-si).getReg(); + if (LV.KillsRegister(mi, regC)) { + DEBUG(std::cerr << "2addr: COMMUTING : " << *mi); + MachineInstr *NewMI = TII.commuteInstruction(mi); + if (NewMI == 0) { + DEBUG(std::cerr << "2addr: COMMUTING FAILED!\n"); + } else { + DEBUG(std::cerr << "2addr: COMMUTED TO: " << *NewMI); + // If the instruction changed to commute it, update livevar. + if (NewMI != mi) { + LV.instructionChanged(mi, NewMI); // Update live variables + mbbi->insert(mi, NewMI); // Insert the new inst + mbbi->erase(mi); // Nuke the old inst. + mi = NewMI; + } + + ++NumCommuted; + regB = regC; + goto InstructionRearranged; } - - ++NumCommuted; - regB = regC; - goto InstructionRearranged; } } + + // If this instruction is potentially convertible to a true + // three-address instruction, + if (TID.Flags & M_CONVERTIBLE_TO_3_ADDR) + // FIXME: This assumes there are no more operands which are tied + // to another register. +#ifndef NDEBUG + for (unsigned i = si+1, e = TII.getNumOperands(opcode); i < e; ++i) + assert(TII.getOperandConstraint(opcode, i, + TargetInstrInfo::TIED_TO) == -1); +#endif + + if (MachineInstr *New = TII.convertToThreeAddress(mi)) { + DEBUG(std::cerr << "2addr: CONVERTING 2-ADDR: " << *mi); + DEBUG(std::cerr << "2addr: TO 3-ADDR: " << *New); + LV.instructionChanged(mi, New); // Update live variables + mbbi->insert(mi, New); // Insert the new inst + mbbi->erase(mi); // Nuke the old inst. + mi = New; + ++NumConvertedTo3Addr; + assert(!TII.isTwoAddrInstr(New->getOpcode()) && + "convertToThreeAddress returned a 2-addr instruction??"); + // Done with this instruction. + break; + } + } + + InstructionRearranged: + const TargetRegisterClass* rc = MF.getSSARegMap()->getRegClass(regA); + MRI.copyRegToReg(*mbbi, mi, regA, regB, rc); + + MachineBasicBlock::iterator prevMi = prior(mi); + DEBUG(std::cerr << "\t\tprepend:\t"; prevMi->print(std::cerr, &TM)); + + // Update live variables for regA + LiveVariables::VarInfo& varInfo = LV.getVarInfo(regA); + varInfo.DefInst = prevMi; + + // update live variables for regB + if (LV.removeVirtualRegisterKilled(regB, mbbi, mi)) + LV.addVirtualRegisterKilled(regB, prevMi); + + if (LV.removeVirtualRegisterDead(regB, mbbi, mi)) + LV.addVirtualRegisterDead(regB, prevMi); + + // replace all occurences of regB with regA + for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) { + if (mi->getOperand(i).isRegister() && + mi->getOperand(i).getReg() == regB) + mi->getOperand(i).setReg(regA); } - // If this instruction is potentially convertible to a true - // three-address instruction, - if (TID.Flags & M_CONVERTIBLE_TO_3_ADDR) - if (MachineInstr *New = TII.convertToThreeAddress(mi)) { - DEBUG(std::cerr << "2addr: CONVERTING 2-ADDR: " << *mi); - DEBUG(std::cerr << "2addr: TO 3-ADDR: " << *New); - LV.instructionChanged(mi, New); // Update live variables - mbbi->insert(mi, New); // Insert the new inst - mbbi->erase(mi); // Nuke the old inst. - mi = New; - ++NumConvertedTo3Addr; - assert(!TII.isTwoAddrInstr(New->getOpcode()) && - "convertToThreeAddress returned a 2-addr instruction??"); - // Done with this instruction. - continue; - } } - InstructionRearranged: - const TargetRegisterClass* rc = MF.getSSARegMap()->getRegClass(regA); - MRI.copyRegToReg(*mbbi, mi, regA, regB, rc); - MachineBasicBlock::iterator prevMi = prior(mi); - DEBUG(std::cerr << "\t\tprepend:\t"; prevMi->print(std::cerr, &TM)); + assert(mi->getOperand(ti).isDef() && mi->getOperand(si).isUse()); + mi->getOperand(ti).setReg(mi->getOperand(si).getReg()); + MadeChange = true; - // Update live variables for regA - LiveVariables::VarInfo& varInfo = LV.getVarInfo(regA); - varInfo.DefInst = prevMi; - - // update live variables for regB - if (LV.removeVirtualRegisterKilled(regB, mbbi, mi)) - LV.addVirtualRegisterKilled(regB, prevMi); - - if (LV.removeVirtualRegisterDead(regB, mbbi, mi)) - LV.addVirtualRegisterDead(regB, prevMi); - - // replace all occurences of regB with regA - for (unsigned i = 1, e = mi->getNumOperands(); i != e; ++i) { - if (mi->getOperand(i).isRegister() && - mi->getOperand(i).getReg() == regB) - mi->getOperand(i).setReg(regA); - } + DEBUG(std::cerr << "\t\trewrite to:\t"; mi->print(std::cerr, &TM)); } - - assert(mi->getOperand(0).isDef() && mi->getOperand(1).isUse()); - mi->getOperand(1).setReg(mi->getOperand(0).getReg()); - MadeChange = true; - - DEBUG(std::cerr << "\t\trewrite to:\t"; mi->print(std::cerr, &TM)); } } diff --git a/lib/CodeGen/VirtRegMap.cpp b/lib/CodeGen/VirtRegMap.cpp index 850c16904e8..911c5c6b792 100644 --- a/lib/CodeGen/VirtRegMap.cpp +++ b/lib/CodeGen/VirtRegMap.cpp @@ -98,7 +98,8 @@ void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI, } ModRef MRInfo; - if (OpNo < 2 && TII.isTwoAddrInstr(OldMI->getOpcode())) { + if (TII.getOperandConstraint(OldMI->getOpcode(), OpNo, + TargetInstrInfo::TIED_TO)) { // Folded a two-address operand. MRInfo = isModRef; } else if (OldMI->getOperand(OpNo).isDef()) { @@ -560,9 +561,11 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { // aren't allowed to modify the reused register. If none of these cases // apply, reuse it. bool CanReuse = true; - if (i == 1 && MI.getOperand(0).isReg() && - MI.getOperand(0).getReg() == VirtReg && - TII->isTwoAddrInstr(MI.getOpcode())) { + int ti = TII->getOperandConstraint(MI.getOpcode(), i, + TargetInstrInfo::TIED_TO); + if (ti != -1 && + MI.getOperand(ti).isReg() && + MI.getOperand(ti).getReg() == VirtReg) { // Okay, we have a two address operand. We can reuse this physreg as // long as we are allowed to clobber the value. CanReuse = Spills.canClobberPhysReg(StackSlot); @@ -818,8 +821,9 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { // If this def is part of a two-address operand, make sure to execute // the store from the correct physical register. unsigned PhysReg; - if (i == 0 && TII->isTwoAddrInstr(MI.getOpcode())) - PhysReg = MI.getOperand(1).getReg(); + int TiedOp = TII->getTiedToSrcOperand(MI.getOpcode(), i); + if (TiedOp != -1) + PhysReg = MI.getOperand(TiedOp).getReg(); else PhysReg = VRM.getPhys(VirtReg);