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Make requiresRegisterScavenging determination on a per MachineFunction basis.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34711 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2007-02-28 00:59:19 +00:00
parent 63f8a21545
commit 36230cdda4
5 changed files with 15 additions and 13 deletions
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2
include/llvm/Target/MRegisterInfo.h
View File

@ -394,7 +394,7 @@ public:
/// requiresRegisterScavenging - returns true if the target requires (and
/// can make use of) the register scavenger.
virtual bool requiresRegisterScavenging() const {
virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
return false;
}

2
lib/CodeGen/PrologEpilogInserter.cpp
View File

@ -442,7 +442,7 @@ void PEI::replaceFrameIndices(MachineFunction &Fn) {
const TargetMachine &TM = Fn.getTarget();
assert(TM.getRegisterInfo() && "TM::getRegisterInfo() must be implemented!");
const MRegisterInfo &MRI = *TM.getRegisterInfo();
RegScavenger *RS = MRI.requiresRegisterScavenging() ? new RegScavenger():NULL;
RegScavenger *RS=MRI.requiresRegisterScavenging(Fn) ? new RegScavenger():NULL;
for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
if (RS) RS->reset(BB);

6
lib/Target/ARM/ARMRegisterInfo.cpp
View File

@ -326,8 +326,10 @@ BitVector ARMRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
return Reserved;
}
bool ARMRegisterInfo::requiresRegisterScavenging() const {
return EnableScavenging;
bool
ARMRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
return EnableScavenging && !AFI->isThumbFunction();
}
/// hasFP - Return true if the specified function should have a dedicated frame

2
lib/Target/ARM/ARMRegisterInfo.h
View File

@ -74,7 +74,7 @@ public:
BitVector getReservedRegs(const MachineFunction &MF) const;
bool requiresRegisterScavenging() const;
bool requiresRegisterScavenging(const MachineFunction &MF) const;
bool hasFP(const MachineFunction &MF) const;

16
lib/Target/ARM/ARMRegisterInfo.td
View File

@ -163,14 +163,14 @@ def GPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6,
return THUMB_GPR_AO;
if (Subtarget.useThumbBacktraces()) {
if (Subtarget.isR9Reserved())
return RI->requiresRegisterScavenging() ? ARM_GPR_AO_8 : ARM_GPR_AO_4;
return RI->requiresRegisterScavenging(MF) ? ARM_GPR_AO_8:ARM_GPR_AO_4;
else
return RI->requiresRegisterScavenging() ? ARM_GPR_AO_7 : ARM_GPR_AO_3;
return RI->requiresRegisterScavenging(MF) ? ARM_GPR_AO_7:ARM_GPR_AO_3;
} else {
if (Subtarget.isR9Reserved())
return RI->requiresRegisterScavenging() ? ARM_GPR_AO_6 : ARM_GPR_AO_2;
return RI->requiresRegisterScavenging(MF) ? ARM_GPR_AO_6:ARM_GPR_AO_2;
else
return RI->requiresRegisterScavenging() ? ARM_GPR_AO_5 : ARM_GPR_AO_1;
return RI->requiresRegisterScavenging(MF) ? ARM_GPR_AO_5:ARM_GPR_AO_1;
}
}
@ -184,24 +184,24 @@ def GPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6,
I = THUMB_GPR_AO + (sizeof(THUMB_GPR_AO)/sizeof(unsigned));
else if (Subtarget.useThumbBacktraces()) {
if (Subtarget.isR9Reserved()) {
if (RI->requiresRegisterScavenging())
if (RI->requiresRegisterScavenging(MF))
I = ARM_GPR_AO_8 + (sizeof(ARM_GPR_AO_8)/sizeof(unsigned));
else
I = ARM_GPR_AO_4 + (sizeof(ARM_GPR_AO_4)/sizeof(unsigned));
} else {
if (RI->requiresRegisterScavenging())
if (RI->requiresRegisterScavenging(MF))
I = ARM_GPR_AO_7 + (sizeof(ARM_GPR_AO_7)/sizeof(unsigned));
else
I = ARM_GPR_AO_3 + (sizeof(ARM_GPR_AO_3)/sizeof(unsigned));
}
} else {
if (Subtarget.isR9Reserved()) {
if (RI->requiresRegisterScavenging())
if (RI->requiresRegisterScavenging(MF))
I = ARM_GPR_AO_6 + (sizeof(ARM_GPR_AO_6)/sizeof(unsigned));
else
I = ARM_GPR_AO_2 + (sizeof(ARM_GPR_AO_2)/sizeof(unsigned));
} else {
if (RI->requiresRegisterScavenging())
if (RI->requiresRegisterScavenging(MF))
I = ARM_GPR_AO_5 + (sizeof(ARM_GPR_AO_5)/sizeof(unsigned));
else
I = ARM_GPR_AO_1 + (sizeof(ARM_GPR_AO_1)/sizeof(unsigned));