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Make requiresRegisterScavenging determination on a per MachineFunction basis.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34711 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -394,7 +394,7 @@ public:
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/// requiresRegisterScavenging - returns true if the target requires (and
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/// requiresRegisterScavenging - returns true if the target requires (and
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/// can make use of) the register scavenger.
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/// can make use of) the register scavenger.
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virtual bool requiresRegisterScavenging() const {
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virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
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return false;
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return false;
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}
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}
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@ -442,7 +442,7 @@ void PEI::replaceFrameIndices(MachineFunction &Fn) {
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const TargetMachine &TM = Fn.getTarget();
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const TargetMachine &TM = Fn.getTarget();
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assert(TM.getRegisterInfo() && "TM::getRegisterInfo() must be implemented!");
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assert(TM.getRegisterInfo() && "TM::getRegisterInfo() must be implemented!");
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const MRegisterInfo &MRI = *TM.getRegisterInfo();
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const MRegisterInfo &MRI = *TM.getRegisterInfo();
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RegScavenger *RS = MRI.requiresRegisterScavenging() ? new RegScavenger():NULL;
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RegScavenger *RS=MRI.requiresRegisterScavenging(Fn) ? new RegScavenger():NULL;
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for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
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for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
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if (RS) RS->reset(BB);
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if (RS) RS->reset(BB);
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@ -326,8 +326,10 @@ BitVector ARMRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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return Reserved;
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return Reserved;
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}
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}
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bool ARMRegisterInfo::requiresRegisterScavenging() const {
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bool
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return EnableScavenging;
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ARMRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
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const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
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return EnableScavenging && !AFI->isThumbFunction();
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}
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}
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/// hasFP - Return true if the specified function should have a dedicated frame
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/// hasFP - Return true if the specified function should have a dedicated frame
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@ -74,7 +74,7 @@ public:
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BitVector getReservedRegs(const MachineFunction &MF) const;
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BitVector getReservedRegs(const MachineFunction &MF) const;
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bool requiresRegisterScavenging() const;
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bool requiresRegisterScavenging(const MachineFunction &MF) const;
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bool hasFP(const MachineFunction &MF) const;
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bool hasFP(const MachineFunction &MF) const;
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@ -163,14 +163,14 @@ def GPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6,
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return THUMB_GPR_AO;
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return THUMB_GPR_AO;
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if (Subtarget.useThumbBacktraces()) {
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if (Subtarget.useThumbBacktraces()) {
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if (Subtarget.isR9Reserved())
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if (Subtarget.isR9Reserved())
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return RI->requiresRegisterScavenging() ? ARM_GPR_AO_8 : ARM_GPR_AO_4;
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return RI->requiresRegisterScavenging(MF) ? ARM_GPR_AO_8:ARM_GPR_AO_4;
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else
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else
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return RI->requiresRegisterScavenging() ? ARM_GPR_AO_7 : ARM_GPR_AO_3;
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return RI->requiresRegisterScavenging(MF) ? ARM_GPR_AO_7:ARM_GPR_AO_3;
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} else {
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} else {
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if (Subtarget.isR9Reserved())
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if (Subtarget.isR9Reserved())
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return RI->requiresRegisterScavenging() ? ARM_GPR_AO_6 : ARM_GPR_AO_2;
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return RI->requiresRegisterScavenging(MF) ? ARM_GPR_AO_6:ARM_GPR_AO_2;
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else
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else
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return RI->requiresRegisterScavenging() ? ARM_GPR_AO_5 : ARM_GPR_AO_1;
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return RI->requiresRegisterScavenging(MF) ? ARM_GPR_AO_5:ARM_GPR_AO_1;
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}
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}
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}
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}
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@ -184,24 +184,24 @@ def GPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6,
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I = THUMB_GPR_AO + (sizeof(THUMB_GPR_AO)/sizeof(unsigned));
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I = THUMB_GPR_AO + (sizeof(THUMB_GPR_AO)/sizeof(unsigned));
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else if (Subtarget.useThumbBacktraces()) {
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else if (Subtarget.useThumbBacktraces()) {
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if (Subtarget.isR9Reserved()) {
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if (Subtarget.isR9Reserved()) {
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if (RI->requiresRegisterScavenging())
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if (RI->requiresRegisterScavenging(MF))
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I = ARM_GPR_AO_8 + (sizeof(ARM_GPR_AO_8)/sizeof(unsigned));
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I = ARM_GPR_AO_8 + (sizeof(ARM_GPR_AO_8)/sizeof(unsigned));
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else
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else
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I = ARM_GPR_AO_4 + (sizeof(ARM_GPR_AO_4)/sizeof(unsigned));
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I = ARM_GPR_AO_4 + (sizeof(ARM_GPR_AO_4)/sizeof(unsigned));
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} else {
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} else {
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if (RI->requiresRegisterScavenging())
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if (RI->requiresRegisterScavenging(MF))
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I = ARM_GPR_AO_7 + (sizeof(ARM_GPR_AO_7)/sizeof(unsigned));
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I = ARM_GPR_AO_7 + (sizeof(ARM_GPR_AO_7)/sizeof(unsigned));
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else
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else
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I = ARM_GPR_AO_3 + (sizeof(ARM_GPR_AO_3)/sizeof(unsigned));
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I = ARM_GPR_AO_3 + (sizeof(ARM_GPR_AO_3)/sizeof(unsigned));
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}
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}
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} else {
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} else {
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if (Subtarget.isR9Reserved()) {
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if (Subtarget.isR9Reserved()) {
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if (RI->requiresRegisterScavenging())
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if (RI->requiresRegisterScavenging(MF))
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I = ARM_GPR_AO_6 + (sizeof(ARM_GPR_AO_6)/sizeof(unsigned));
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I = ARM_GPR_AO_6 + (sizeof(ARM_GPR_AO_6)/sizeof(unsigned));
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else
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else
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I = ARM_GPR_AO_2 + (sizeof(ARM_GPR_AO_2)/sizeof(unsigned));
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I = ARM_GPR_AO_2 + (sizeof(ARM_GPR_AO_2)/sizeof(unsigned));
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} else {
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} else {
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if (RI->requiresRegisterScavenging())
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if (RI->requiresRegisterScavenging(MF))
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I = ARM_GPR_AO_5 + (sizeof(ARM_GPR_AO_5)/sizeof(unsigned));
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I = ARM_GPR_AO_5 + (sizeof(ARM_GPR_AO_5)/sizeof(unsigned));
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else
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else
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I = ARM_GPR_AO_1 + (sizeof(ARM_GPR_AO_1)/sizeof(unsigned));
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I = ARM_GPR_AO_1 + (sizeof(ARM_GPR_AO_1)/sizeof(unsigned));
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