mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-02-21 21:29:41 +00:00
move CC Lowering stuff to its own public interface
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34655 91177308-0d34-0410-b5e6-96231b3b80d8
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149
include/llvm/CodeGen/CallingConvLower.h
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149
include/llvm/CodeGen/CallingConvLower.h
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@ -0,0 +1,149 @@
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//===-- llvm/CallingConvLower.h - Calling Conventions -----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Chris Lattner and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the CCState and CCValAssign classes, used for lowering
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// and implementing calling conventions.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_CALLINGCONVLOWER_H
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#define LLVM_CODEGEN_CALLINGCONVLOWER_H
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/ValueTypes.h"
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namespace llvm {
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class MRegisterInfo;
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/// CCState - This class holds information needed while lowering arguments and
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/// return values. It captures which registers are already assigned and which
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/// stack slots are used. It provides accessors to allocate these values.
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class CCState {
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unsigned StackOffset;
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const MRegisterInfo &MRI;
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SmallVector<uint32_t, 16> UsedRegs;
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public:
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CCState(const MRegisterInfo &mri);
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unsigned getNextStackOffset() const { return StackOffset; }
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/// isAllocated - Return true if the specified register (or an alias) is
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/// allocated.
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bool isAllocated(unsigned Reg) const {
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return UsedRegs[Reg/32] & (1 << (Reg&31));
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}
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/// getFirstUnallocated - Return the first unallocated register in the set, or
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/// NumRegs if they are all allocated.
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unsigned getFirstUnallocated(const unsigned *Regs, unsigned NumRegs) const {
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for (unsigned i = 0; i != NumRegs; ++i)
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if (!isAllocated(Regs[i]))
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return i;
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return NumRegs;
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}
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/// AllocateReg - Attempt to allocate one of the specified registers. If none
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/// are available, return zero. Otherwise, return the first one available,
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/// marking it and any aliases as allocated.
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unsigned AllocateReg(const unsigned *Regs, unsigned NumRegs) {
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unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs);
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if (FirstUnalloc == NumRegs)
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return 0; // Didn't find the reg.
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// Mark the register and any aliases as allocated.
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unsigned Reg = Regs[FirstUnalloc];
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MarkAllocated(Reg);
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return Reg;
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}
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/// AllocateStack - Allocate a chunk of stack space with the specified size
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/// and alignment.
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unsigned AllocateStack(unsigned Size, unsigned Align) {
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assert(Align && ((Align-1) & Align) == 0); // Align is power of 2.
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StackOffset = ((StackOffset + Align-1) & ~(Align-1));
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unsigned Result = StackOffset;
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StackOffset += Size;
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return Result;
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}
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private:
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/// MarkAllocated - Mark a register and all of its aliases as allocated.
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void MarkAllocated(unsigned Reg);
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};
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/// CCValAssign - Represent assignment of one arg/retval to a location.
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class CCValAssign {
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public:
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enum LocInfo {
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Full, // The value fills the full location.
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SExt, // The value is sign extended in the location.
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ZExt, // The value is zero extended in the location.
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AExt // The value is extended with undefined upper bits.
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// TODO: a subset of the value is in the location.
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};
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private:
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/// ValNo - This is the value number begin assigned (e.g. an argument number).
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unsigned ValNo;
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/// Loc is either a stack offset or a register number.
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unsigned Loc;
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/// isMem - True if this is a memory loc, false if it is a register loc.
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bool isMem : 1;
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/// Information about how the value is assigned.
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LocInfo HTP : 7;
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/// ValVT - The type of the value being assigned.
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MVT::ValueType ValVT : 8;
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/// LocVT - The type of the location being assigned to.
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MVT::ValueType LocVT : 8;
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public:
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static CCValAssign getReg(unsigned ValNo, MVT::ValueType ValVT,
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unsigned RegNo, MVT::ValueType LocVT,
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LocInfo HTP) {
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CCValAssign Ret;
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Ret.ValNo = ValNo;
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Ret.Loc = RegNo;
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Ret.isMem = false;
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Ret.HTP = HTP;
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Ret.ValVT = ValVT;
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Ret.LocVT = LocVT;
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return Ret;
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}
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static CCValAssign getMem(unsigned ValNo, MVT::ValueType ValVT,
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unsigned Offset, MVT::ValueType LocVT,
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LocInfo HTP) {
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CCValAssign Ret;
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Ret.ValNo = ValNo;
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Ret.Loc = Offset;
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Ret.isMem = true;
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Ret.HTP = HTP;
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Ret.ValVT = ValVT;
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Ret.LocVT = LocVT;
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return Ret;
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}
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unsigned getValNo() const { return ValNo; }
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MVT::ValueType getValVT() const { return ValVT; }
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bool isRegLoc() const { return !isMem; }
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bool isMemLoc() const { return isMem; }
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unsigned getLocReg() const { assert(isRegLoc()); return Loc; }
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unsigned getLocMemOffset() const { assert(isMemLoc()); return Loc; }
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MVT::ValueType getLocVT() const { return LocVT; }
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LocInfo getLocInfo() const { return HTP; }
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};
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} // end namespace llvm
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#endif
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34
lib/CodeGen/SelectionDAG/CallingConvLower.cpp
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34
lib/CodeGen/SelectionDAG/CallingConvLower.cpp
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//===-- llvm/CallingConvLower.cpp - Calling Conventions -------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Chris Lattner and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the CCState class, used for lowering and implementing
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// calling conventions.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/Target/MRegisterInfo.h"
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using namespace llvm;
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CCState::CCState(const MRegisterInfo &mri) : MRI(mri) {
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// No stack is used.
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StackOffset = 0;
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UsedRegs.resize(MRI.getNumRegs());
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}
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/// MarkAllocated - Mark a register and all of its aliases as allocated.
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void CCState::MarkAllocated(unsigned Reg) {
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UsedRegs[Reg/32] |= 1 << (Reg&31);
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if (const unsigned *RegAliases = MRI.getAliasSet(Reg))
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for (; (Reg = *RegAliases); ++RegAliases)
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UsedRegs[Reg/32] |= 1 << (Reg&31);
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}
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@ -24,6 +24,7 @@
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#include "llvm/Intrinsics.h"
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#include "llvm/Intrinsics.h"
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#include "llvm/ADT/VectorExtras.h"
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#include "llvm/ADT/VectorExtras.h"
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#include "llvm/Analysis/ScalarEvolutionExpressions.h"
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#include "llvm/Analysis/ScalarEvolutionExpressions.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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@ -1058,140 +1059,11 @@ SDOperand X86TargetLowering::LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG,
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// X86-64 C Calling Convention implementation
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// X86-64 C Calling Convention implementation
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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class CallingConvState {
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unsigned StackOffset;
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const MRegisterInfo &MRI;
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SmallVector<uint32_t, 16> UsedRegs;
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public:
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CallingConvState(const MRegisterInfo &mri) : MRI(mri) {
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// No stack is used.
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StackOffset = 0;
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UsedRegs.resize(MRI.getNumRegs());
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}
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unsigned getNextStackOffset() const { return StackOffset; }
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/// isAllocated - Return true if the specified register (or an alias) is
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/// allocated.
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bool isAllocated(unsigned Reg) const {
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return UsedRegs[Reg/32] & (1 << (Reg&31));
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}
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/// getFirstUnallocated - Return the first unallocated register in the set, or
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/// NumRegs if they are all allocated.
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unsigned getFirstUnallocated(const unsigned *Regs, unsigned NumRegs) const {
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for (unsigned i = 0; i != NumRegs; ++i)
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if (!isAllocated(Regs[i]))
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return i;
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return NumRegs;
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}
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/// AllocateReg - Attempt to allocate one of the specified registers. If none
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/// are available, return zero. Otherwise, return the first one available,
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/// marking it and any aliases as allocated.
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unsigned AllocateReg(const unsigned *Regs, unsigned NumRegs) {
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unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs);
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if (FirstUnalloc == NumRegs)
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return 0; // Didn't find the reg.
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// Mark the register and any aliases as allocated.
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unsigned Reg = Regs[FirstUnalloc];
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MarkAllocated(Reg);
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if (const unsigned *RegAliases = MRI.getAliasSet(Reg))
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for (; *RegAliases; ++RegAliases)
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MarkAllocated(*RegAliases);
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return Reg;
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}
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/// AllocateStack - Allocate a chunk of stack space with the specified size
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/// and alignment.
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unsigned AllocateStack(unsigned Size, unsigned Align) {
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assert(Align && ((Align-1) & Align) == 0); // Align is power of 2.
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StackOffset = ((StackOffset + Align-1) & ~(Align-1));
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unsigned Result = StackOffset;
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StackOffset += Size;
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return Result;
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}
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private:
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void MarkAllocated(unsigned Reg) {
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UsedRegs[Reg/32] |= 1 << (Reg&31);
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}
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};
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/// CCValAssign - Represent assignment of one arg/retval to a location.
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class CCValAssign {
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public:
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enum LocInfo {
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Full, // The value fills the full location.
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SExt, // The value is sign extended in the location.
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ZExt, // The value is zero extended in the location.
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AExt // The value is extended with undefined upper bits.
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// TODO: a subset of the value is in the location.
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};
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private:
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/// ValNo - This is the value number begin assigned (e.g. an argument number).
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unsigned ValNo;
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/// Loc is either a stack offset or a register number.
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unsigned Loc;
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/// isMem - True if this is a memory loc, false if it is a register loc.
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bool isMem : 1;
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/// Information about how the value is assigned.
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LocInfo HTP : 7;
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/// ValVT - The type of the value being assigned.
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MVT::ValueType ValVT : 8;
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/// LocVT - The type of the location being assigned to.
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MVT::ValueType LocVT : 8;
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public:
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static CCValAssign getReg(unsigned ValNo, MVT::ValueType ValVT,
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unsigned RegNo, MVT::ValueType LocVT,
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LocInfo HTP) {
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CCValAssign Ret;
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Ret.ValNo = ValNo;
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Ret.Loc = RegNo;
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Ret.isMem = false;
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Ret.HTP = HTP;
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Ret.ValVT = ValVT;
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Ret.LocVT = LocVT;
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return Ret;
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}
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static CCValAssign getMem(unsigned ValNo, MVT::ValueType ValVT,
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unsigned Offset, MVT::ValueType LocVT,
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LocInfo HTP) {
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CCValAssign Ret;
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Ret.ValNo = ValNo;
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Ret.Loc = Offset;
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Ret.isMem = true;
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Ret.HTP = HTP;
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Ret.ValVT = ValVT;
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Ret.LocVT = LocVT;
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return Ret;
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}
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unsigned getValNo() const { return ValNo; }
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MVT::ValueType getValVT() const { return ValVT; }
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bool isRegLoc() const { return !isMem; }
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bool isMemLoc() const { return isMem; }
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unsigned getLocReg() const { assert(isRegLoc()); return Loc; }
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unsigned getLocMemOffset() const { assert(isMemLoc()); return Loc; }
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MVT::ValueType getLocVT() const { return LocVT; }
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LocInfo getLocInfo() const { return HTP; }
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};
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/// X86_64_CCC_AssignArgument - Implement the X86-64 C Calling Convention.
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/// X86_64_CCC_AssignArgument - Implement the X86-64 C Calling Convention.
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static void X86_64_CCC_AssignArgument(unsigned ValNo,
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static void X86_64_CCC_AssignArgument(unsigned ValNo,
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MVT::ValueType ArgVT, unsigned ArgFlags,
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MVT::ValueType ArgVT, unsigned ArgFlags,
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CallingConvState &State,
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CCState &State,
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SmallVector<CCValAssign, 16> &Locs) {
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SmallVector<CCValAssign, 16> &Locs) {
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MVT::ValueType LocVT = ArgVT;
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MVT::ValueType LocVT = ArgVT;
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CCValAssign::LocInfo LocInfo = CCValAssign::Full;
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CCValAssign::LocInfo LocInfo = CCValAssign::Full;
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@ -1278,18 +1150,23 @@ X86TargetLowering::LowerX86_64CCCArguments(SDOperand Op, SelectionDAG &DAG) {
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SmallVector<SDOperand, 8> ArgValues;
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SmallVector<SDOperand, 8> ArgValues;
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CallingConvState CCState(*getTargetMachine().getRegisterInfo());
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CCState CCInfo(*getTargetMachine().getRegisterInfo());
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SmallVector<CCValAssign, 16> ArgLocs;
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SmallVector<CCValAssign, 16> ArgLocs;
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for (unsigned i = 0; i != NumArgs; ++i) {
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for (unsigned i = 0; i != NumArgs; ++i) {
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MVT::ValueType ArgVT = Op.getValue(i).getValueType();
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MVT::ValueType ArgVT = Op.getValue(i).getValueType();
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unsigned ArgFlags = cast<ConstantSDNode>(Op.getOperand(3+i))->getValue();
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unsigned ArgFlags = cast<ConstantSDNode>(Op.getOperand(3+i))->getValue();
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X86_64_CCC_AssignArgument(i, ArgVT, ArgFlags, CCState, ArgLocs);
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X86_64_CCC_AssignArgument(i, ArgVT, ArgFlags, CCInfo, ArgLocs);
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}
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}
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unsigned LastVal = ~0U;
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for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
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for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
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CCValAssign &VA = ArgLocs[i];
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CCValAssign &VA = ArgLocs[i];
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// TODO: If an arg is passed in two places (e.g. reg and stack), skip later
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// places.
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assert(VA.getValNo() != LastVal &&
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"Don't support value assigned to multiple locs yet");
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LastVal = VA.getValNo();
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if (VA.isRegLoc()) {
|
if (VA.isRegLoc()) {
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MVT::ValueType RegVT = VA.getLocVT();
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MVT::ValueType RegVT = VA.getLocVT();
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||||||
@ -1335,13 +1212,13 @@ X86TargetLowering::LowerX86_64CCCArguments(SDOperand Op, SelectionDAG &DAG) {
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|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
unsigned StackSize = CCState.getNextStackOffset();
|
unsigned StackSize = CCInfo.getNextStackOffset();
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||||||
|
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||||||
// If the function takes variable number of arguments, make a frame index for
|
// If the function takes variable number of arguments, make a frame index for
|
||||||
// the start of the first vararg value... for expansion of llvm.va_start.
|
// the start of the first vararg value... for expansion of llvm.va_start.
|
||||||
if (isVarArg) {
|
if (isVarArg) {
|
||||||
unsigned NumIntRegs = CCState.getFirstUnallocated(GPR64ArgRegs, 6);
|
unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 6);
|
||||||
unsigned NumXMMRegs = CCState.getFirstUnallocated(XMMArgRegs, 8);
|
unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
|
||||||
|
|
||||||
// For X86-64, if there are vararg parameters that are passed via
|
// For X86-64, if there are vararg parameters that are passed via
|
||||||
// registers, then we must store them to their spots on the stack so they
|
// registers, then we must store them to their spots on the stack so they
|
||||||
@ -1403,17 +1280,17 @@ X86TargetLowering::LowerX86_64CCCCallTo(SDOperand Op, SelectionDAG &DAG,
|
|||||||
SDOperand Callee = Op.getOperand(4);
|
SDOperand Callee = Op.getOperand(4);
|
||||||
unsigned NumOps = (Op.getNumOperands() - 5) / 2;
|
unsigned NumOps = (Op.getNumOperands() - 5) / 2;
|
||||||
|
|
||||||
CallingConvState CCState(*getTargetMachine().getRegisterInfo());
|
CCState CCInfo(*getTargetMachine().getRegisterInfo());
|
||||||
SmallVector<CCValAssign, 16> ArgLocs;
|
SmallVector<CCValAssign, 16> ArgLocs;
|
||||||
|
|
||||||
for (unsigned i = 0; i != NumOps; ++i) {
|
for (unsigned i = 0; i != NumOps; ++i) {
|
||||||
MVT::ValueType ArgVT = Op.getOperand(5+2*i).getValueType();
|
MVT::ValueType ArgVT = Op.getOperand(5+2*i).getValueType();
|
||||||
unsigned ArgFlags =cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue();
|
unsigned ArgFlags =cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue();
|
||||||
X86_64_CCC_AssignArgument(i, ArgVT, ArgFlags, CCState, ArgLocs);
|
X86_64_CCC_AssignArgument(i, ArgVT, ArgFlags, CCInfo, ArgLocs);
|
||||||
}
|
}
|
||||||
|
|
||||||
// Get a count of how many bytes are to be pushed on the stack.
|
// Get a count of how many bytes are to be pushed on the stack.
|
||||||
unsigned NumBytes = CCState.getNextStackOffset();
|
unsigned NumBytes = CCInfo.getNextStackOffset();
|
||||||
Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
|
Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
|
||||||
|
|
||||||
SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
|
SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
|
||||||
@ -1422,14 +1299,8 @@ X86TargetLowering::LowerX86_64CCCCallTo(SDOperand Op, SelectionDAG &DAG,
|
|||||||
SDOperand StackPtr;
|
SDOperand StackPtr;
|
||||||
|
|
||||||
// Walk the register/memloc assignments, inserting copies/loads.
|
// Walk the register/memloc assignments, inserting copies/loads.
|
||||||
unsigned LastVal = ~0U;
|
|
||||||
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
|
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
|
||||||
CCValAssign &VA = ArgLocs[i];
|
CCValAssign &VA = ArgLocs[i];
|
||||||
|
|
||||||
assert(VA.getValNo() != LastVal &&
|
|
||||||
"Don't support value assigned to multiple locs yet");
|
|
||||||
LastVal = VA.getValNo();
|
|
||||||
|
|
||||||
SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
|
SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
|
||||||
|
|
||||||
// Promote the value if needed.
|
// Promote the value if needed.
|
||||||
@ -1486,7 +1357,7 @@ X86TargetLowering::LowerX86_64CCCCallTo(SDOperand Op, SelectionDAG &DAG,
|
|||||||
X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
|
X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
|
||||||
X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
|
X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
|
||||||
};
|
};
|
||||||
unsigned NumXMMRegs = CCState.getFirstUnallocated(XMMArgRegs, 8);
|
unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
|
||||||
|
|
||||||
Chain = DAG.getCopyToReg(Chain, X86::AL,
|
Chain = DAG.getCopyToReg(Chain, X86::AL,
|
||||||
DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
|
DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
|
||||||
|
Loading…
x
Reference in New Issue
Block a user