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add FP compares and implicit register defs to the dag isel

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24118 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Duraid Madina 2005-10-31 01:42:11 +00:00
parent a088734a24
commit 363aff2f3c
2 changed files with 45 additions and 23 deletions
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4
lib/Target/IA64/IA64InstrFormats.td
View File

@ -72,4 +72,8 @@ class RawForm<bits<4> opcode, bits<26> rest, dag OL, string asmstr> :
class PseudoInstIA64<dag OL, string nm> : InstIA64<0, OL, nm> { class PseudoInstIA64<dag OL, string nm> : InstIA64<0, OL, nm> {
} }
class PseudoInstIA64_DAG<dag OL, string nm, list<dag> pattern>
: InstIA64<0, OL, nm> {
let Pattern = pattern;
}

64
lib/Target/IA64/IA64InstrInfo.td
View File

@ -200,7 +200,7 @@ def : Pat<(mulhu GR:$src1, GR:$src2),
// load constants of various sizes // FIXME: prettyprint -ve constants // load constants of various sizes // FIXME: prettyprint -ve constants
def : Pat<(i64 immSExt14:$imm), (ADDS r0, immSExt14:$imm)>; def : Pat<(i64 immSExt14:$imm), (ADDS r0, immSExt14:$imm)>;
def : Pat<(i64 imm64:$imm), (MOVL imm64:$imm)>; def : Pat<(i64 imm64:$imm), (MOVL imm64:$imm)>;
// TODO: def : Pat<(i1 1), (MOV p0)>; // TODO: def : Pat<(i1 1), (<stuff>)>;
def AND : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2), def AND : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
"and $dst = $src1, $src2;;", "and $dst = $src1, $src2;;",
@ -290,11 +290,51 @@ def CMPGEU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
"cmp.geu $dst, p0 = $src1, $src2;;", "cmp.geu $dst, p0 = $src1, $src2;;",
[(set PR:$dst, (setuge GR:$src1, GR:$src2))]>; [(set PR:$dst, (setuge GR:$src1, GR:$src2))]>;
// and we do the whole thing again for FP compares!
def FCMPEQ : AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
"fcmp.eq $dst, p0 = $src1, $src2;;",
[(set PR:$dst, (seteq FP:$src1, FP:$src2))]>;
def FCMPGT : AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
"fcmp.gt $dst, p0 = $src1, $src2;;",
[(set PR:$dst, (setgt FP:$src1, FP:$src2))]>;
def FCMPGE : AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
"fcmp.ge $dst, p0 = $src1, $src2;;",
[(set PR:$dst, (setge FP:$src1, FP:$src2))]>;
def FCMPLT : AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
"fcmp.lt $dst, p0 = $src1, $src2;;",
[(set PR:$dst, (setlt FP:$src1, FP:$src2))]>;
def FCMPLE : AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
"fcmp.le $dst, p0 = $src1, $src2;;",
[(set PR:$dst, (setle FP:$src1, FP:$src2))]>;
def FCMPNE : AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
"fcmp.neq $dst, p0 = $src1, $src2;;",
[(set PR:$dst, (setne FP:$src1, FP:$src2))]>;
def FCMPLTU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
"fcmp.ltu $dst, p0 = $src1, $src2;;",
[(set PR:$dst, (setult FP:$src1, FP:$src2))]>;
def FCMPGTU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
"fcmp.gtu $dst, p0 = $src1, $src2;;",
[(set PR:$dst, (setugt FP:$src1, FP:$src2))]>;
def FCMPLEU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
"fcmp.leu $dst, p0 = $src1, $src2;;",
[(set PR:$dst, (setule FP:$src1, FP:$src2))]>;
def FCMPGEU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
"fcmp.geu $dst, p0 = $src1, $src2;;",
[(set PR:$dst, (setuge FP:$src1, FP:$src2))]>;
// TODO: support postincrement (reg, imm9) loads+stores - this needs more // TODO: support postincrement (reg, imm9) loads+stores - this needs more
// tablegen support // tablegen support
def PHI : PseudoInstIA64<(ops variable_ops), "PHI">; def PHI : PseudoInstIA64<(ops variable_ops), "PHI">;
def IDEF : PseudoInstIA64<(ops variable_ops), "// IDEF">; def IDEF : PseudoInstIA64<(ops variable_ops), "// IDEF">;
def IDEF_GR_D : PseudoInstIA64_DAG<(ops GR:$reg), "// $reg = IDEF",
[(set GR:$reg, (undef))]>;
def IDEF_FP_D : PseudoInstIA64_DAG<(ops FP:$reg), "// $reg = IDEF",
[(set FP:$reg, (undef))]>;
def IDEF_PR_D : PseudoInstIA64_DAG<(ops PR:$reg), "// $reg = IDEF",
[(set PR:$reg, (undef))]>;
def IUSE : PseudoInstIA64<(ops variable_ops), "// IUSE">; def IUSE : PseudoInstIA64<(ops variable_ops), "// IUSE">;
def ADJUSTCALLSTACKUP : PseudoInstIA64<(ops variable_ops), def ADJUSTCALLSTACKUP : PseudoInstIA64<(ops variable_ops),
"// ADJUSTCALLSTACKUP">; "// ADJUSTCALLSTACKUP">;
@ -365,28 +405,6 @@ def EXTRU : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm1, u6imm:$imm2),
def DEPZ : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm1, u6imm:$imm2), "dep.z $dst = $src1, $imm1, $imm2;;">; def DEPZ : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm1, u6imm:$imm2), "dep.z $dst = $src1, $imm1, $imm2;;">;
// and we do the whole thing again for FP compares!
def FCMPEQ : AForm<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
"fcmp.eq $dst, p0 = $src1, $src2;;">;
def FCMPGT : AForm<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
"fcmp.gt $dst, p0 = $src1, $src2;;">;
def FCMPGE : AForm<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
"fcmp.ge $dst, p0 = $src1, $src2;;">;
def FCMPLT : AForm<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
"fcmp.lt $dst, p0 = $src1, $src2;;">;
def FCMPLE : AForm<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
"fcmp.le $dst, p0 = $src1, $src2;;">;
def FCMPNE : AForm<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
"fcmp.neq $dst, p0 = $src1, $src2;;">;
def FCMPLTU : AForm<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
"fcmp.ltu $dst, p0 = $src1, $src2;;">;
def FCMPGTU : AForm<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
"fcmp.gtu $dst, p0 = $src1, $src2;;">;
def FCMPLEU : AForm<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
"fcmp.leu $dst, p0 = $src1, $src2;;">;
def FCMPGEU : AForm<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
"fcmp.geu $dst, p0 = $src1, $src2;;">;
def PCMPEQOR : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2, PR:$qp), def PCMPEQOR : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2, PR:$qp),
"($qp) cmp.eq.or $dst, p0 = $src1, $src2;;">; "($qp) cmp.eq.or $dst, p0 = $src1, $src2;;">;
def PCMPEQUNC : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2, PR:$qp), def PCMPEQUNC : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2, PR:$qp),