mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-07-18 10:24:45 +00:00
replace TRI->isVirtualRegister() with TargetRegisterInfo::isVirtualRegister()
per customary usage git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83137 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
@@ -242,7 +242,7 @@ unsigned RegScavenger::findSurvivorReg(MachineBasicBlock::iterator MI,
|
||||
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
||||
const MachineOperand &MO = MI->getOperand(i);
|
||||
if (!MO.isReg() || MO.isUndef() || !MO.getReg() ||
|
||||
TRI->isVirtualRegister(MO.getReg()))
|
||||
TargetRegisterInfo::isVirtualRegister(MO.getReg()))
|
||||
continue;
|
||||
Candidates.reset(MO.getReg());
|
||||
for (const unsigned *R = TRI->getAliasSet(MO.getReg()); *R; R++)
|
||||
@@ -280,7 +280,8 @@ unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
|
||||
// Exclude all the registers being used by the instruction.
|
||||
for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
|
||||
MachineOperand &MO = I->getOperand(i);
|
||||
if (MO.isReg() && MO.getReg() != 0 && !TRI->isVirtualRegister(MO.getReg()))
|
||||
if (MO.isReg() && MO.getReg() != 0 &&
|
||||
!TargetRegisterInfo::isVirtualRegister(MO.getReg()))
|
||||
Candidates.reset(MO.getReg());
|
||||
}
|
||||
|
||||
|
Reference in New Issue
Block a user