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replace TRI->isVirtualRegister() with TargetRegisterInfo::isVirtualRegister()

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per customary usage

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83137 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2009-09-30 01:47:59 +00:00
parent d1a5ca6cb1
commit 366e021fb2
2 changed files with 4 additions and 5 deletions
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4
lib/CodeGen/PrologEpilogInserter.cpp
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@ -731,8 +731,6 @@ void PEI::replaceFrameIndices(MachineFunction &Fn) {
/// with physical registers. Use the register scavenger to find an /// with physical registers. Use the register scavenger to find an
/// appropriate register to use. /// appropriate register to use.
void PEI::scavengeFrameVirtualRegs(MachineFunction &Fn) { void PEI::scavengeFrameVirtualRegs(MachineFunction &Fn) {
const TargetRegisterInfo *TRI = Fn.getTarget().getRegisterInfo();
// Run through the instructions and find any virtual registers. // Run through the instructions and find any virtual registers.
for (MachineFunction::iterator BB = Fn.begin(), for (MachineFunction::iterator BB = Fn.begin(),
E = Fn.end(); BB != E; ++BB) { E = Fn.end(); BB != E; ++BB) {
@ -746,7 +744,7 @@ void PEI::scavengeFrameVirtualRegs(MachineFunction &Fn) {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
if (MI->getOperand(i).isReg()) { if (MI->getOperand(i).isReg()) {
unsigned Reg = MI->getOperand(i).getReg(); unsigned Reg = MI->getOperand(i).getReg();
if (Reg == 0 || !TRI->isVirtualRegister(Reg)) if (Reg == 0 || !TargetRegisterInfo::isVirtualRegister(Reg))
continue; continue;
// If we already have a scratch for this virtual register, use it // If we already have a scratch for this virtual register, use it

5
lib/CodeGen/RegisterScavenging.cpp
View File

@ -242,7 +242,7 @@ unsigned RegScavenger::findSurvivorReg(MachineBasicBlock::iterator MI,
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i); const MachineOperand &MO = MI->getOperand(i);
if (!MO.isReg() || MO.isUndef() || !MO.getReg() || if (!MO.isReg() || MO.isUndef() || !MO.getReg() ||
TRI->isVirtualRegister(MO.getReg())) TargetRegisterInfo::isVirtualRegister(MO.getReg()))
continue; continue;
Candidates.reset(MO.getReg()); Candidates.reset(MO.getReg());
for (const unsigned *R = TRI->getAliasSet(MO.getReg()); *R; R++) for (const unsigned *R = TRI->getAliasSet(MO.getReg()); *R; R++)
@ -280,7 +280,8 @@ unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
// Exclude all the registers being used by the instruction. // Exclude all the registers being used by the instruction.
for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) { for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
MachineOperand &MO = I->getOperand(i); MachineOperand &MO = I->getOperand(i);
if (MO.isReg() && MO.getReg() != 0 && !TRI->isVirtualRegister(MO.getReg())) if (MO.isReg() && MO.getReg() != 0 &&
!TargetRegisterInfo::isVirtualRegister(MO.getReg()))
Candidates.reset(MO.getReg()); Candidates.reset(MO.getReg());
} }