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R600/SI: Add basic support for more integer vector types.

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v1i32, v2i32, v8i32 and v16i32.

Only add VGPR register classes for integer vector types, to avoid attempts
copying from VGPR to SGPR registers, which is not possible.

Patch By: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174632 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard
2013-02-07 17:02:09 +00:00
parent 66f535a273
commit 36ba909184
5 changed files with 110 additions and 11 deletions
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51
lib/Target/R600/AMDGPUInstructions.td
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@@ -191,6 +191,19 @@ class Insert_Element <ValueType elem_type, ValueType vec_type,
>;
// Vector Build pattern
class Vector1_Build <ValueType vecType, RegisterClass vectorClass,
ValueType elemType, RegisterClass elemClass> : Pat <
(vecType (build_vector (elemType elemClass:$src))),
(vecType elemClass:$src)
>;
class Vector2_Build <ValueType vecType, RegisterClass vectorClass,
ValueType elemType, RegisterClass elemClass> : Pat <
(vecType (build_vector (elemType elemClass:$sub0), (elemType elemClass:$sub1))),
(INSERT_SUBREG (INSERT_SUBREG
(vecType (IMPLICIT_DEF)), elemClass:$sub0, sub0), elemClass:$sub1, sub1)
>;
class Vector_Build <ValueType vecType, RegisterClass vectorClass,
ValueType elemType, RegisterClass elemClass> : Pat <
(vecType (build_vector (elemType elemClass:$x), (elemType elemClass:$y),
@@ -200,6 +213,44 @@ class Vector_Build <ValueType vecType, RegisterClass vectorClass,
elemClass:$z, sub2), elemClass:$w, sub3)
>;
class Vector8_Build <ValueType vecType, RegisterClass vectorClass,
ValueType elemType, RegisterClass elemClass> : Pat <
(vecType (build_vector (elemType elemClass:$sub0), (elemType elemClass:$sub1),
(elemType elemClass:$sub2), (elemType elemClass:$sub3),
(elemType elemClass:$sub4), (elemType elemClass:$sub5),
(elemType elemClass:$sub6), (elemType elemClass:$sub7))),
(INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG
(INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG
(vecType (IMPLICIT_DEF)), elemClass:$sub0, sub0), elemClass:$sub1, sub1),
elemClass:$sub2, sub2), elemClass:$sub3, sub3),
elemClass:$sub4, sub4), elemClass:$sub5, sub5),
elemClass:$sub6, sub6), elemClass:$sub7, sub7)
>;
class Vector16_Build <ValueType vecType, RegisterClass vectorClass,
ValueType elemType, RegisterClass elemClass> : Pat <
(vecType (build_vector (elemType elemClass:$sub0), (elemType elemClass:$sub1),
(elemType elemClass:$sub2), (elemType elemClass:$sub3),
(elemType elemClass:$sub4), (elemType elemClass:$sub5),
(elemType elemClass:$sub6), (elemType elemClass:$sub7),
(elemType elemClass:$sub8), (elemType elemClass:$sub9),
(elemType elemClass:$sub10), (elemType elemClass:$sub11),
(elemType elemClass:$sub12), (elemType elemClass:$sub13),
(elemType elemClass:$sub14), (elemType elemClass:$sub15))),
(INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG
(INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG
(INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG
(INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG
(vecType (IMPLICIT_DEF)), elemClass:$sub0, sub0), elemClass:$sub1, sub1),
elemClass:$sub2, sub2), elemClass:$sub3, sub3),
elemClass:$sub4, sub4), elemClass:$sub5, sub5),
elemClass:$sub6, sub6), elemClass:$sub7, sub7),
elemClass:$sub8, sub8), elemClass:$sub9, sub9),
elemClass:$sub10, sub10), elemClass:$sub11, sub11),
elemClass:$sub12, sub12), elemClass:$sub13, sub13),
elemClass:$sub14, sub14), elemClass:$sub15, sub15)
>;
// bitconvert pattern
class BitConvert <ValueType dt, ValueType st, RegisterClass rc> : Pat <
(dt (bitconvert (st rc:$src0))),