mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-26 23:29:22 +00:00
Fix type of LUXC1 and SUXC1. These instructions were incorrectly defined as
single-precision load and store. Also avoid selecting LUXC1 and SUXC1 instructions during isel. It is incorrect to map unaligned floating point load/store nodes to these instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161063 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
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53b59d1d97
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36bcc11236
@ -289,21 +289,6 @@ bool MipsDAGToDAGISel::
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SelectAddr(SDNode *Parent, SDValue Addr, SDValue &Base, SDValue &Offset) {
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SelectAddr(SDNode *Parent, SDValue Addr, SDValue &Base, SDValue &Offset) {
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EVT ValTy = Addr.getValueType();
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EVT ValTy = Addr.getValueType();
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// If Parent is an unaligned f32 load or store, select a (base + index)
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// floating point load/store instruction (luxc1 or suxc1).
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const LSBaseSDNode *LS = 0;
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if (Parent && (LS = dyn_cast<LSBaseSDNode>(Parent))) {
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EVT VT = LS->getMemoryVT();
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if (VT.getSizeInBits() / 8 > LS->getAlignment()) {
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assert(TLI.allowsUnalignedMemoryAccesses(VT) &&
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"Unaligned loads/stores not supported for this type.");
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if (VT == MVT::f32)
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return false;
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}
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}
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// if Address is FI, get the TargetFrameIndex.
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// if Address is FI, get the TargetFrameIndex.
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if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
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if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
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@ -362,6 +347,8 @@ SelectAddr(SDNode *Parent, SDValue Addr, SDValue &Base, SDValue &Offset) {
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}
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}
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// If an indexed floating point load/store can be emitted, return false.
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// If an indexed floating point load/store can be emitted, return false.
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const LSBaseSDNode *LS = dyn_cast<LSBaseSDNode>(Parent);
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if (LS &&
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if (LS &&
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(LS->getMemoryVT() == MVT::f32 || LS->getMemoryVT() == MVT::f64) &&
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(LS->getMemoryVT() == MVT::f32 || LS->getMemoryVT() == MVT::f64) &&
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Subtarget.hasMips32r2Or64())
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Subtarget.hasMips32r2Or64())
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@ -314,8 +314,6 @@ bool MipsTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
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case MVT::i64:
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case MVT::i64:
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case MVT::i32:
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case MVT::i32:
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return true;
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return true;
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case MVT::f32:
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return Subtarget->hasMips32r2Or64();
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default:
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default:
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return false;
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return false;
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}
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}
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@ -101,7 +101,7 @@ class FPStore<bits<6> op, string opstr, RegisterClass RC, Operand MemOpnd>:
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}
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}
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// FP indexed load.
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// FP indexed load.
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class FPIdxLoad<bits<6> funct, string opstr, RegisterClass DRC,
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class FPIdxLoad<bits<6> funct, string opstr, RegisterClass DRC,
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RegisterClass PRC, PatFrag FOp>:
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RegisterClass PRC, SDPatternOperator FOp = null_frag>:
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FFMemIdx<funct, (outs DRC:$fd), (ins PRC:$base, PRC:$index),
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FFMemIdx<funct, (outs DRC:$fd), (ins PRC:$base, PRC:$index),
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!strconcat(opstr, "\t$fd, $index($base)"),
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!strconcat(opstr, "\t$fd, $index($base)"),
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[(set DRC:$fd, (FOp (add PRC:$base, PRC:$index)))]> {
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[(set DRC:$fd, (FOp (add PRC:$base, PRC:$index)))]> {
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@ -110,7 +110,7 @@ class FPIdxLoad<bits<6> funct, string opstr, RegisterClass DRC,
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// FP indexed store.
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// FP indexed store.
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class FPIdxStore<bits<6> funct, string opstr, RegisterClass DRC,
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class FPIdxStore<bits<6> funct, string opstr, RegisterClass DRC,
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RegisterClass PRC, PatFrag FOp>:
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RegisterClass PRC, SDPatternOperator FOp= null_frag>:
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FFMemIdx<funct, (outs), (ins DRC:$fs, PRC:$base, PRC:$index),
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FFMemIdx<funct, (outs), (ins DRC:$fs, PRC:$base, PRC:$index),
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!strconcat(opstr, "\t$fs, $index($base)"),
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!strconcat(opstr, "\t$fs, $index($base)"),
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[(FOp DRC:$fs, (add PRC:$base, PRC:$index))]> {
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[(FOp DRC:$fs, (add PRC:$base, PRC:$index))]> {
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@ -283,9 +283,7 @@ let Predicates = [NotN64, NotMips64, HasStandardEncoding] in {
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// Indexed loads and stores.
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// Indexed loads and stores.
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let Predicates = [HasMips32r2Or64, HasStandardEncoding] in {
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let Predicates = [HasMips32r2Or64, HasStandardEncoding] in {
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def LWXC1 : FPIdxLoad<0x0, "lwxc1", FGR32, CPURegs, load_a>;
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def LWXC1 : FPIdxLoad<0x0, "lwxc1", FGR32, CPURegs, load_a>;
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def LUXC1 : FPIdxLoad<0x5, "luxc1", FGR32, CPURegs, load_u>;
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def SWXC1 : FPIdxStore<0x8, "swxc1", FGR32, CPURegs, store_a>;
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def SWXC1 : FPIdxStore<0x8, "swxc1", FGR32, CPURegs, store_a>;
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def SUXC1 : FPIdxStore<0xd, "suxc1", FGR32, CPURegs, store_u>;
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}
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}
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let Predicates = [HasMips32r2, NotMips64, HasStandardEncoding] in {
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let Predicates = [HasMips32r2, NotMips64, HasStandardEncoding] in {
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@ -301,13 +299,23 @@ let Predicates = [HasMips64, NotN64, HasStandardEncoding], DecoderNamespace="Mip
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// n64
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// n64
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let Predicates = [IsN64, HasStandardEncoding], isCodeGenOnly=1 in {
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let Predicates = [IsN64, HasStandardEncoding], isCodeGenOnly=1 in {
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def LWXC1_P8 : FPIdxLoad<0x0, "lwxc1", FGR32, CPU64Regs, load_a>;
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def LWXC1_P8 : FPIdxLoad<0x0, "lwxc1", FGR32, CPU64Regs, load_a>;
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def LUXC1_P8 : FPIdxLoad<0x5, "luxc1", FGR32, CPU64Regs, load_u>;
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def LDXC164_P8 : FPIdxLoad<0x1, "ldxc1", FGR64, CPU64Regs, load_a>;
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def LDXC164_P8 : FPIdxLoad<0x1, "ldxc1", FGR64, CPU64Regs, load_a>;
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def SWXC1_P8 : FPIdxStore<0x8, "swxc1", FGR32, CPU64Regs, store_a>;
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def SWXC1_P8 : FPIdxStore<0x8, "swxc1", FGR32, CPU64Regs, store_a>;
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def SUXC1_P8 : FPIdxStore<0xd, "suxc1", FGR32, CPU64Regs, store_u>;
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def SDXC164_P8 : FPIdxStore<0x9, "sdxc1", FGR64, CPU64Regs, store_a>;
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def SDXC164_P8 : FPIdxStore<0x9, "sdxc1", FGR64, CPU64Regs, store_a>;
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}
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}
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// Load/store doubleword indexed unaligned.
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let Predicates = [NotMips64, HasStandardEncoding] in {
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def LUXC1 : FPIdxLoad<0x5, "luxc1", AFGR64, CPURegs>;
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def SUXC1 : FPIdxStore<0xd, "suxc1", AFGR64, CPURegs>;
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}
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let Predicates = [HasMips64, HasStandardEncoding],
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DecoderNamespace="Mips64" in {
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def LUXC164 : FPIdxLoad<0x5, "luxc1", FGR64, CPURegs>;
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def SUXC164 : FPIdxStore<0xd, "suxc1", FGR64, CPURegs>;
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}
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/// Floating-point Aritmetic
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/// Floating-point Aritmetic
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defm FADD : FFR2P_M<0x00, "add", fadd, 1>;
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defm FADD : FFR2P_M<0x00, "add", fadd, 1>;
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defm FDIV : FFR2P_M<0x03, "div", fdiv>;
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defm FDIV : FFR2P_M<0x03, "div", fdiv>;
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@ -466,17 +474,3 @@ let Predicates = [IsFP64bit, HasStandardEncoding] in {
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def : MipsPat<(f32 (fround FGR64:$src)), (CVT_S_D64 FGR64:$src)>;
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def : MipsPat<(f32 (fround FGR64:$src)), (CVT_S_D64 FGR64:$src)>;
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def : MipsPat<(f64 (fextend FGR32:$src)), (CVT_D64_S FGR32:$src)>;
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def : MipsPat<(f64 (fextend FGR32:$src)), (CVT_D64_S FGR32:$src)>;
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}
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}
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// Patterns for unaligned floating point loads and stores.
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let Predicates = [HasMips32r2Or64, NotN64, HasStandardEncoding] in {
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def : MipsPat<(f32 (load_u CPURegs:$addr)), (LUXC1 CPURegs:$addr, ZERO)>;
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def : MipsPat<(store_u FGR32:$src, CPURegs:$addr),
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(SUXC1 FGR32:$src, CPURegs:$addr, ZERO)>;
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}
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let Predicates = [IsN64, HasStandardEncoding] in {
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def : MipsPat<(f32 (load_u CPU64Regs:$addr)),
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(LUXC1_P8 CPU64Regs:$addr, ZERO_64)>;
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def : MipsPat<(store_u FGR32:$src, CPU64Regs:$addr),
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(SUXC1_P8 FGR32:$src, CPU64Regs:$addr, ZERO_64)>;
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}
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@ -28,7 +28,7 @@ entry:
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define float @foo2(i32 %b, i32 %c) nounwind readonly {
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define float @foo2(i32 %b, i32 %c) nounwind readonly {
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entry:
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entry:
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; CHECK: luxc1
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; CHECK-NOT: luxc1
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%arrayidx1 = getelementptr inbounds [4 x %struct.S]* @s, i32 0, i32 %b, i32 0, i32 %c
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%arrayidx1 = getelementptr inbounds [4 x %struct.S]* @s, i32 0, i32 %b, i32 0, i32 %c
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%0 = load float* %arrayidx1, align 1
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%0 = load float* %arrayidx1, align 1
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ret float %0
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ret float %0
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@ -54,7 +54,7 @@ entry:
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define void @foo5(i32 %b, i32 %c) nounwind {
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define void @foo5(i32 %b, i32 %c) nounwind {
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entry:
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entry:
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; CHECK: suxc1
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; CHECK-NOT: suxc1
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%0 = load float* @gf, align 4
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%0 = load float* @gf, align 4
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%arrayidx1 = getelementptr inbounds [4 x %struct.S]* @s, i32 0, i32 %b, i32 0, i32 %c
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%arrayidx1 = getelementptr inbounds [4 x %struct.S]* @s, i32 0, i32 %b, i32 0, i32 %c
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store float %0, float* %arrayidx1, align 1
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store float %0, float* %arrayidx1, align 1
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@ -64,7 +64,7 @@ entry:
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define double @foo6(i32 %b, i32 %c) nounwind readonly {
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define double @foo6(i32 %b, i32 %c) nounwind readonly {
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entry:
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entry:
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; CHECK: foo6
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; CHECK: foo6
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; CHECK-NOT: ldxc1
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; CHECK-NOT: luxc1
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%arrayidx1 = getelementptr inbounds [4 x %struct.S2]* @s2, i32 0, i32 %b, i32 0, i32 %c
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%arrayidx1 = getelementptr inbounds [4 x %struct.S2]* @s2, i32 0, i32 %b, i32 0, i32 %c
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%0 = load double* %arrayidx1, align 1
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%0 = load double* %arrayidx1, align 1
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ret double %0
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ret double %0
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@ -73,7 +73,7 @@ entry:
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define void @foo7(i32 %b, i32 %c) nounwind {
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define void @foo7(i32 %b, i32 %c) nounwind {
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entry:
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entry:
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; CHECK: foo7
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; CHECK: foo7
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; CHECK-NOT: sdxc1
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; CHECK-NOT: suxc1
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%0 = load double* @gd, align 8
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%0 = load double* @gd, align 8
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%arrayidx1 = getelementptr inbounds [4 x %struct.S2]* @s2, i32 0, i32 %b, i32 0, i32 %c
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%arrayidx1 = getelementptr inbounds [4 x %struct.S2]* @s2, i32 0, i32 %b, i32 0, i32 %c
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store double %0, double* %arrayidx1, align 1
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store double %0, double* %arrayidx1, align 1
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@ -83,7 +83,7 @@ entry:
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define float @foo8() nounwind readonly {
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define float @foo8() nounwind readonly {
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entry:
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entry:
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; CHECK: foo8
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; CHECK: foo8
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; CHECK: luxc1
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; CHECK-NOT: luxc1
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%0 = load float* getelementptr inbounds (%struct.S3* @s3, i32 0, i32 1), align 1
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%0 = load float* getelementptr inbounds (%struct.S3* @s3, i32 0, i32 1), align 1
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ret float %0
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ret float %0
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}
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}
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@ -91,7 +91,7 @@ entry:
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define void @foo9(float %f) nounwind {
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define void @foo9(float %f) nounwind {
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entry:
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entry:
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; CHECK: foo9
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; CHECK: foo9
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; CHECK: suxc1
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; CHECK-NOT: suxc1
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store float %f, float* getelementptr inbounds (%struct.S3* @s3, i32 0, i32 1), align 1
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store float %f, float* getelementptr inbounds (%struct.S3* @s3, i32 0, i32 1), align 1
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ret void
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ret void
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}
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}
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@ -30,7 +30,7 @@ entry:
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define float @foo2(i32 %b, i32 %c) nounwind readonly {
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define float @foo2(i32 %b, i32 %c) nounwind readonly {
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entry:
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entry:
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; CHECK: luxc1
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; CHECK-NOT: luxc1
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%idxprom = zext i32 %c to i64
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%idxprom = zext i32 %c to i64
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%idxprom1 = zext i32 %b to i64
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%idxprom1 = zext i32 %b to i64
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%arrayidx2 = getelementptr inbounds [4 x %struct.S]* @s, i64 0, i64 %idxprom1, i32 0, i64 %idxprom
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%arrayidx2 = getelementptr inbounds [4 x %struct.S]* @s, i64 0, i64 %idxprom1, i32 0, i64 %idxprom
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@ -60,7 +60,7 @@ entry:
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define void @foo5(i32 %b, i32 %c) nounwind {
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define void @foo5(i32 %b, i32 %c) nounwind {
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entry:
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entry:
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; CHECK: suxc1
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; CHECK-NOT: suxc1
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%0 = load float* @gf, align 4
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%0 = load float* @gf, align 4
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%idxprom = zext i32 %c to i64
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%idxprom = zext i32 %c to i64
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%idxprom1 = zext i32 %b to i64
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%idxprom1 = zext i32 %b to i64
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@ -72,7 +72,7 @@ entry:
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define double @foo6(i32 %b, i32 %c) nounwind readonly {
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define double @foo6(i32 %b, i32 %c) nounwind readonly {
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entry:
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entry:
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; CHECK: foo6
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; CHECK: foo6
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; CHECK-NOT: ldxc1
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; CHECK-NOT: luxc1
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%idxprom = zext i32 %c to i64
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%idxprom = zext i32 %c to i64
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%idxprom1 = zext i32 %b to i64
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%idxprom1 = zext i32 %b to i64
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%arrayidx2 = getelementptr inbounds [4 x %struct.S2]* @s2, i64 0, i64 %idxprom1, i32 0, i64 %idxprom
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%arrayidx2 = getelementptr inbounds [4 x %struct.S2]* @s2, i64 0, i64 %idxprom1, i32 0, i64 %idxprom
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@ -83,7 +83,7 @@ entry:
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define void @foo7(i32 %b, i32 %c) nounwind {
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define void @foo7(i32 %b, i32 %c) nounwind {
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entry:
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entry:
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; CHECK: foo7
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; CHECK: foo7
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; CHECK-NOT: sdxc1
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; CHECK-NOT: suxc1
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%0 = load double* @gd, align 8
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%0 = load double* @gd, align 8
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%idxprom = zext i32 %c to i64
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%idxprom = zext i32 %c to i64
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%idxprom1 = zext i32 %b to i64
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%idxprom1 = zext i32 %b to i64
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@ -95,7 +95,7 @@ entry:
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define float @foo8() nounwind readonly {
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define float @foo8() nounwind readonly {
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entry:
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entry:
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; CHECK: foo8
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; CHECK: foo8
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; CHECK: luxc1
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; CHECK-NOT: luxc1
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%0 = load float* getelementptr inbounds (%struct.S3* @s3, i64 0, i32 1), align 1
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%0 = load float* getelementptr inbounds (%struct.S3* @s3, i64 0, i32 1), align 1
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ret float %0
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ret float %0
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}
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}
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@ -103,7 +103,7 @@ entry:
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define void @foo9(float %f) nounwind {
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define void @foo9(float %f) nounwind {
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entry:
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entry:
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; CHECK: foo9
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; CHECK: foo9
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; CHECK: suxc1
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; CHECK-NOT: suxc1
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store float %f, float* getelementptr inbounds (%struct.S3* @s3, i64 0, i32 1), align 1
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store float %f, float* getelementptr inbounds (%struct.S3* @s3, i64 0, i32 1), align 1
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ret void
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ret void
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}
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}
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