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Simplify and rearrange long shift code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17861 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2979,23 +2979,28 @@ void X86ISel::emitShiftOperation(MachineBasicBlock *MBB,
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DestReg).addReg(SrcReg ).addReg(SrcReg+1).addImm(Amount);
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BuildMI(*MBB, IP, Opc[2],2,DestReg+1).addReg(SrcReg+1).addImm(Amount);
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}
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} else if (Amount == 32) {
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if (isLeftShift) {
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BuildMI(*MBB, IP, X86::MOV32rr, 1, DestReg+1).addReg(SrcReg);
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BuildMI(*MBB, IP, X86::MOV32ri, 1, DestReg).addImm(0);
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} else {
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BuildMI(*MBB, IP, X86::MOV32rr, 1, DestReg).addReg(SrcReg);
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if (!isSigned) {
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BuildMI(*MBB, IP, X86::MOV32ri, 1, DestReg+1).addImm(0);
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} else {
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BuildMI(*MBB, IP, X86::SAR32ri, 2,
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DestReg+1).addReg(SrcReg).addImm(31);
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}
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}
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} else { // Shifting more than 32 bits
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Amount -= 32;
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if (isLeftShift) {
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if (Amount != 0) {
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BuildMI(*MBB, IP, X86::SHL32ri, 2,
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DestReg + 1).addReg(SrcReg).addImm(Amount);
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} else {
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BuildMI(*MBB, IP, X86::MOV32rr, 1, DestReg+1).addReg(SrcReg);
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}
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BuildMI(*MBB, IP, X86::SHL32ri, 2,
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DestReg + 1).addReg(SrcReg).addImm(Amount);
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BuildMI(*MBB, IP, X86::MOV32ri, 1, DestReg).addImm(0);
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} else {
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if (Amount != 0) {
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BuildMI(*MBB, IP, isSigned ? X86::SAR32ri : X86::SHR32ri, 2,
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DestReg).addReg(SrcReg+1).addImm(Amount);
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} else {
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BuildMI(*MBB, IP, X86::MOV32rr, 1, DestReg).addReg(SrcReg+1);
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}
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BuildMI(*MBB, IP, isSigned ? X86::SAR32ri : X86::SHR32ri, 2,
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DestReg).addReg(SrcReg+1).addImm(Amount);
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BuildMI(*MBB, IP, X86::MOV32ri, 1, DestReg+1).addImm(0);
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}
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}
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