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During bittest switch lowering emit shift in the test block, which should (theoretically)
allow us to generate more efficient code. We don't do this now though :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63027 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1416,14 +1416,8 @@ void SelectionDAGLowering::visitBitTestHeader(BitTestBlock &B) {
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else
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ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB);
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// Make desired shift
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SDValue SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(),
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DAG.getConstant(1, TLI.getPointerTy()),
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ShiftOp);
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unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy());
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SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), SwitchReg, SwitchVal);
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B.Reg = SwitchReg;
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B.Reg = FuncInfo.MakeReg(TLI.getShiftAmountTy());
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SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), B.Reg, ShiftOp);
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// Set NextBlock to be the MBB immediately after the current one, if any.
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// This is used to avoid emitting unnecessary branches to the next block.
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@ -1453,10 +1447,14 @@ void SelectionDAGLowering::visitBitTestHeader(BitTestBlock &B) {
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void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
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unsigned Reg,
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BitTestCase &B) {
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// Emit bit tests and jumps
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SDValue SwitchVal = DAG.getCopyFromReg(getControlRoot(), Reg,
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TLI.getPointerTy());
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// Make desired shift
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SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), Reg,
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TLI.getShiftAmountTy());
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SDValue SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(),
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DAG.getConstant(1, TLI.getPointerTy()),
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ShiftOp);
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// Emit bit tests and jumps
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SDValue AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(), SwitchVal,
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DAG.getConstant(B.Mask, TLI.getPointerTy()));
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SDValue AndCmp = DAG.getSetCC(TLI.getSetCCResultType(AndOp.getValueType()),
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