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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-09-30 04:56:49 +00:00
[mips][msa] Added support for matching pckev, and pckod from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191306 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders
parent
f515964d36
commit
3706eda52c
@ -230,6 +230,8 @@ const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
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case MipsISD::ILVOD: return "MipsISD::ILVOD";
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case MipsISD::ILVL: return "MipsISD::ILVL";
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case MipsISD::ILVR: return "MipsISD::ILVR";
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case MipsISD::PCKEV: return "MipsISD::PCKEV";
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case MipsISD::PCKOD: return "MipsISD::PCKOD";
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default: return NULL;
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}
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}
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@ -179,6 +179,8 @@ namespace llvm {
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ILVOD, // Interleave odd elements
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ILVL, // Interleave left elements
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ILVR, // Interleave right elements
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PCKEV, // Pack even elements
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PCKOD, // Pack odd elements
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// Combined (XOR (OR $a, $b), -1)
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VNOR,
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@ -48,6 +48,8 @@ def MipsILVEV : SDNode<"MipsISD::ILVEV", SDT_ILV>;
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def MipsILVOD : SDNode<"MipsISD::ILVOD", SDT_ILV>;
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def MipsILVL : SDNode<"MipsISD::ILVL", SDT_ILV>;
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def MipsILVR : SDNode<"MipsISD::ILVR", SDT_ILV>;
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def MipsPCKEV : SDNode<"MipsISD::PCKEV", SDT_ILV>;
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def MipsPCKOD : SDNode<"MipsISD::PCKOD", SDT_ILV>;
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def vsetcc : SDNode<"ISD::SETCC", SDT_VSetCC>;
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def vfsetcc : SDNode<"ISD::SETCC", SDT_VFSetCC>;
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@ -2060,15 +2062,15 @@ class OR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128D>;
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class ORI_B_DESC : MSA_I8_DESC_BASE<"ori.b", or, vsplati8_uimm8, MSA128B>;
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class PCKEV_B_DESC : MSA_3R_DESC_BASE<"pckev.b", int_mips_pckev_b, MSA128B>;
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class PCKEV_H_DESC : MSA_3R_DESC_BASE<"pckev.h", int_mips_pckev_h, MSA128H>;
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class PCKEV_W_DESC : MSA_3R_DESC_BASE<"pckev.w", int_mips_pckev_w, MSA128W>;
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class PCKEV_D_DESC : MSA_3R_DESC_BASE<"pckev.d", int_mips_pckev_d, MSA128D>;
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class PCKEV_B_DESC : MSA_3R_DESC_BASE<"pckev.b", MipsPCKEV, MSA128B>;
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class PCKEV_H_DESC : MSA_3R_DESC_BASE<"pckev.h", MipsPCKEV, MSA128H>;
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class PCKEV_W_DESC : MSA_3R_DESC_BASE<"pckev.w", MipsPCKEV, MSA128W>;
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class PCKEV_D_DESC : MSA_3R_DESC_BASE<"pckev.d", MipsPCKEV, MSA128D>;
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class PCKOD_B_DESC : MSA_3R_DESC_BASE<"pckod.b", int_mips_pckod_b, MSA128B>;
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class PCKOD_H_DESC : MSA_3R_DESC_BASE<"pckod.h", int_mips_pckod_h, MSA128H>;
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class PCKOD_W_DESC : MSA_3R_DESC_BASE<"pckod.w", int_mips_pckod_w, MSA128W>;
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class PCKOD_D_DESC : MSA_3R_DESC_BASE<"pckod.d", int_mips_pckod_d, MSA128D>;
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class PCKOD_B_DESC : MSA_3R_DESC_BASE<"pckod.b", MipsPCKOD, MSA128B>;
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class PCKOD_H_DESC : MSA_3R_DESC_BASE<"pckod.h", MipsPCKOD, MSA128H>;
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class PCKOD_W_DESC : MSA_3R_DESC_BASE<"pckod.w", MipsPCKOD, MSA128W>;
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class PCKOD_D_DESC : MSA_3R_DESC_BASE<"pckod.d", MipsPCKOD, MSA128D>;
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class PCNT_B_DESC : MSA_2R_DESC_BASE<"pcnt.b", ctpop, MSA128B>;
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class PCNT_H_DESC : MSA_2R_DESC_BASE<"pcnt.h", ctpop, MSA128H>;
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@ -1447,6 +1447,18 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
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case Intrinsic::mips_ori_b:
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return lowerMSABinaryImmIntr(Op, DAG, ISD::OR,
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lowerMSASplatImm(Op, 2, DAG));
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case Intrinsic::mips_pckev_b:
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case Intrinsic::mips_pckev_h:
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case Intrinsic::mips_pckev_w:
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case Intrinsic::mips_pckev_d:
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return DAG.getNode(MipsISD::PCKEV, SDLoc(Op), Op->getValueType(0),
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Op->getOperand(1), Op->getOperand(2));
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case Intrinsic::mips_pckod_b:
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case Intrinsic::mips_pckod_h:
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case Intrinsic::mips_pckod_w:
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case Intrinsic::mips_pckod_d:
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return DAG.getNode(MipsISD::PCKOD, SDLoc(Op), Op->getValueType(0),
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Op->getOperand(1), Op->getOperand(2));
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case Intrinsic::mips_pcnt_b:
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case Intrinsic::mips_pcnt_h:
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case Intrinsic::mips_pcnt_w:
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@ -1951,6 +1963,58 @@ static SDValue lowerVECTOR_SHUFFLE_ILVR(SDValue Op, EVT ResTy,
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Op->getOperand(1));
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}
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// Lower VECTOR_SHUFFLE into PCKEV (if possible).
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//
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// PCKEV copies the even elements of each vector into the result vector.
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//
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// It is possible to lower into PCKEV when the mask takes the form:
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// <0, 2, 4, ..., n, n+2, n+4, ...>
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// where n is the number of elements in the vector.
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//
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// When undef's appear in the mask they are treated as if they were whatever
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// value is necessary in order to fit the above form.
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static SDValue lowerVECTOR_SHUFFLE_PCKEV(SDValue Op, EVT ResTy,
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SmallVector<int, 16> Indices,
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SelectionDAG &DAG) {
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assert ((Indices.size() % 2) == 0);
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int Idx = 0;
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for (unsigned i = 0; i < Indices.size(); ++i) {
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if (Indices[i] != -1 && Indices[i] != Idx)
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return SDValue();
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Idx += 2;
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}
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return DAG.getNode(MipsISD::PCKEV, SDLoc(Op), ResTy, Op->getOperand(0),
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Op->getOperand(1));
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}
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// Lower VECTOR_SHUFFLE into PCKOD (if possible).
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//
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// PCKOD copies the odd elements of each vector into the result vector.
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//
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// It is possible to lower into PCKOD when the mask takes the form:
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// <1, 3, 5, ..., n+1, n+3, n+5, ...>
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// where n is the number of elements in the vector.
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//
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// When undef's appear in the mask they are treated as if they were whatever
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// value is necessary in order to fit the above form.
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static SDValue lowerVECTOR_SHUFFLE_PCKOD(SDValue Op, EVT ResTy,
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SmallVector<int, 16> Indices,
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SelectionDAG &DAG) {
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assert ((Indices.size() % 2) == 0);
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int Idx = 1;
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for (unsigned i = 0; i < Indices.size(); ++i) {
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if (Indices[i] != -1 && Indices[i] != Idx)
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return SDValue();
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Idx += 2;
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}
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return DAG.getNode(MipsISD::PCKOD, SDLoc(Op), ResTy, Op->getOperand(0),
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Op->getOperand(1));
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}
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// Lower VECTOR_SHUFFLE into VSHF.
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//
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// This mostly consists of converting the shuffle indices in Indices into a
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@ -2031,6 +2095,12 @@ SDValue MipsSETargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
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if (Result.getNode())
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return Result;
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Result = lowerVECTOR_SHUFFLE_ILVR(Op, ResTy, Indices, DAG);
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if (Result.getNode())
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return Result;
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Result = lowerVECTOR_SHUFFLE_PCKEV(Op, ResTy, Indices, DAG);
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if (Result.getNode())
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return Result;
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Result = lowerVECTOR_SHUFFLE_PCKOD(Op, ResTy, Indices, DAG);
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if (Result.getNode())
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return Result;
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return lowerVECTOR_SHUFFLE_VSHF(Op, ResTy, Indices, DAG);
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@ -616,3 +616,135 @@ define void @ilvr_v2i64_0(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind
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ret void
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; CHECK: .size ilvr_v2i64_0
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}
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define void @pckev_v16i8_0(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
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; CHECK: pckev_v16i8_0:
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%1 = load <16 x i8>* %a
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; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
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%2 = load <16 x i8>* %b
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; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
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%3 = shufflevector <16 x i8> %1, <16 x i8> %2,
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<16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
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; CHECK-DAG: pckev.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
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store <16 x i8> %3, <16 x i8>* %c
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; CHECK-DAG: st.b [[R3]], 0($4)
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ret void
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; CHECK: .size pckev_v16i8_0
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}
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define void @pckev_v8i16_0(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
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; CHECK: pckev_v8i16_0:
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%1 = load <8 x i16>* %a
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; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
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%2 = load <8 x i16>* %b
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; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
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%3 = shufflevector <8 x i16> %1, <8 x i16> %2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
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; CHECK-DAG: pckev.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
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store <8 x i16> %3, <8 x i16>* %c
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; CHECK-DAG: st.h [[R3]], 0($4)
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ret void
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; CHECK: .size pckev_v8i16_0
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}
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define void @pckev_v4i32_0(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
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; CHECK: pckev_v4i32_0:
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%1 = load <4 x i32>* %a
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; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
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%2 = load <4 x i32>* %b
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; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
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%3 = shufflevector <4 x i32> %1, <4 x i32> %2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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; CHECK-DAG: pckev.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
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store <4 x i32> %3, <4 x i32>* %c
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; CHECK-DAG: st.w [[R3]], 0($4)
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ret void
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; CHECK: .size pckev_v4i32_0
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}
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define void @pckev_v2i64_0(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
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; CHECK: pckev_v2i64_0:
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%1 = load <2 x i64>* %a
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; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
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%2 = load <2 x i64>* %b
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; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
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%3 = shufflevector <2 x i64> %1, <2 x i64> %2, <2 x i32> <i32 0, i32 2>
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; pckev.d and ilvev.d are equivalent for v2i64
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; CHECK-DAG: ilvev.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
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store <2 x i64> %3, <2 x i64>* %c
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; CHECK-DAG: st.d [[R3]], 0($4)
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ret void
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; CHECK: .size pckev_v2i64_0
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}
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define void @pckod_v16i8_0(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
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; CHECK: pckod_v16i8_0:
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%1 = load <16 x i8>* %a
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; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
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%2 = load <16 x i8>* %b
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; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
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%3 = shufflevector <16 x i8> %1, <16 x i8> %2,
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<16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
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; CHECK-DAG: pckod.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
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store <16 x i8> %3, <16 x i8>* %c
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; CHECK-DAG: st.b [[R3]], 0($4)
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ret void
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; CHECK: .size pckod_v16i8_0
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}
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define void @pckod_v8i16_0(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
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; CHECK: pckod_v8i16_0:
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%1 = load <8 x i16>* %a
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; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
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%2 = load <8 x i16>* %b
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; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
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%3 = shufflevector <8 x i16> %1, <8 x i16> %2, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
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; CHECK-DAG: pckod.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
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store <8 x i16> %3, <8 x i16>* %c
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; CHECK-DAG: st.h [[R3]], 0($4)
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ret void
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; CHECK: .size pckod_v8i16_0
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}
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define void @pckod_v4i32_0(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
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; CHECK: pckod_v4i32_0:
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%1 = load <4 x i32>* %a
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; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
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%2 = load <4 x i32>* %b
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; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
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%3 = shufflevector <4 x i32> %1, <4 x i32> %2, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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; CHECK-DAG: pckod.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
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store <4 x i32> %3, <4 x i32>* %c
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; CHECK-DAG: st.w [[R3]], 0($4)
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ret void
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; CHECK: .size pckod_v4i32_0
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}
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define void @pckod_v2i64_0(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
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; CHECK: pckod_v2i64_0:
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%1 = load <2 x i64>* %a
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; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
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%2 = load <2 x i64>* %b
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; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
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%3 = shufflevector <2 x i64> %1, <2 x i64> %2, <2 x i32> <i32 1, i32 3>
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; pckod.d and ilvod.d are equivalent for v2i64
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; CHECK-DAG: ilvod.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
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store <2 x i64> %3, <2 x i64>* %c
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; CHECK-DAG: st.d [[R3]], 0($4)
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ret void
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; CHECK: .size pckod_v2i64_0
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}
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