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Add memory barrier intrinsic support for ARM. Moving towards adding the atomic operations intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91003 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -377,7 +377,7 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
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setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
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else
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setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
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setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
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setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
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if (!Subtarget->hasV6Ops() && !Subtarget->isThumb2()) {
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
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@ -500,6 +500,9 @@ const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
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case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
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case ARMISD::MEMBARRIER: return "ARMISD::MEMBARRIER";
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case ARMISD::SYNCBARRIER: return "ARMISD::SYNCBARRIER";
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case ARMISD::VCEQ: return "ARMISD::VCEQ";
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case ARMISD::VCGE: return "ARMISD::VCGE";
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case ARMISD::VCGEU: return "ARMISD::VCGEU";
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@ -1470,6 +1473,21 @@ ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
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}
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}
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static SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) {
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DebugLoc dl = Op.getDebugLoc();
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SDValue Op5 = Op.getOperand(5);
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SDValue Res;
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unsigned isDeviceBarrier = cast<ConstantSDNode>(Op5)->getZExtValue();
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if (isDeviceBarrier) {
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Res = DAG.getNode(ARMISD::SYNCBARRIER, dl, MVT::Other,
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Op.getOperand(0));
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} else {
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Res = DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other,
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Op.getOperand(0));
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}
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return Res;
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}
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static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
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unsigned VarArgsFrameIndex) {
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// vastart just stores the address of the VarArgsFrameIndex slot into the
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@ -2972,6 +2990,7 @@ SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
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case ISD::BR_JT: return LowerBR_JT(Op, DAG);
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case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
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case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex);
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case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG);
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case ISD::SINT_TO_FP:
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case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
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case ISD::FP_TO_SINT:
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@ -72,6 +72,9 @@ namespace llvm {
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DYN_ALLOC, // Dynamic allocation on the stack.
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MEMBARRIER, // Memory barrier
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SYNCBARRIER, // Memory sync barrier
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VCEQ, // Vector compare equal.
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VCGE, // Vector compare greater than or equal.
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VCGEU, // Vector compare unsigned greater than or equal.
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@ -46,6 +46,9 @@ def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
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def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
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def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
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def SDT_ARMMEMBARRIER : SDTypeProfile<0, 0, []>;
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def SDT_ARMSYNCBARRIER : SDTypeProfile<0, 0, []>;
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// Node definitions.
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def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
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def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
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@ -93,6 +96,11 @@ def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>;
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def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
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def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP", SDT_ARMEH_SJLJ_Setjmp>;
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def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
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[SDNPHasChain]>;
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def ARMSyncBarrier : SDNode<"ARMISD::SYNCBARRIER", SDT_ARMMEMBARRIER,
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[SDNPHasChain]>;
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//===----------------------------------------------------------------------===//
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// ARM Instruction Predicate Definitions.
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//
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@ -1561,6 +1569,24 @@ def MOVCCi : AI1<0b1101, (outs GPR:$dst),
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let Inst{25} = 1;
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}
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//===----------------------------------------------------------------------===//
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// Atomic operations intrinsics
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//
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// memory barriers protect the atomic sequences
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let isBarrier = 1 in {
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def Int_MemBarrierV7 : AI<(outs), (ins),
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Pseudo, NoItinerary,
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"dmb", "",
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[(ARMMemBarrier)]>,
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Requires<[HasV7]>;
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def Int_SyncBarrierV7 : AI<(outs), (ins),
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Pseudo, NoItinerary,
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"dsb", "",
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[(ARMSyncBarrier)]>,
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Requires<[HasV7]>;
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}
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//===----------------------------------------------------------------------===//
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// TLS Instructions
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