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[AArch32] Add patterns for VCVT{A,N,P,M}.

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Patterns for lowering libm calls to VCVT{A,N,P,M} are also included.
Phabricator Revision: http://reviews.llvm.org/D5033

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216388 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chad Rosier
2014-08-25 16:56:33 +00:00
parent cc4b123a47
commit 373fc00835
2 changed files with 130 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

22
lib/Target/ARM/ARMInstrVFP.td
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@@ -627,27 +627,30 @@ def : Pat<(f16_to_fp GPR:$a),
def : Pat<(f64 (f16_to_fp GPR:$a)),
(VCVTBHD (COPY_TO_REGCLASS GPR:$a, SPR))>;
multiclass vcvt_inst<string opc, bits<2> rm> {
multiclass vcvt_inst<string opc, bits<2> rm,
SDPatternOperator node = null_frag> {
let PostEncoderMethod = "", DecoderNamespace = "VFPV8" in {
def SS : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0,
(outs SPR:$Sd), (ins SPR:$Sm),
NoItinerary, !strconcat("vcvt", opc, ".s32.f32\t$Sd, $Sm"),
[]>, Requires<[HasFPARMv8]> {
[(set SPR:$Sd, (arm_ftosi (node SPR:$Sm)))]>,
Requires<[HasFPARMv8]> {
let Inst{17-16} = rm;
}
def US : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0,
(outs SPR:$Sd), (ins SPR:$Sm),
NoItinerary, !strconcat("vcvt", opc, ".u32.f32\t$Sd, $Sm"),
[]>, Requires<[HasFPARMv8]> {
[(set SPR:$Sd, (arm_ftoui (node SPR:$Sm)))]>,
Requires<[HasFPARMv8]> {
let Inst{17-16} = rm;
}
def SD : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0,
(outs SPR:$Sd), (ins DPR:$Dm),
NoItinerary, !strconcat("vcvt", opc, ".s32.f64\t$Sd, $Dm"),
[]>, Requires<[HasFPARMv8, HasDPVFP]> {
[(set SPR:$Sd, (arm_ftosi (f64 (node (f64 DPR:$Dm)))))]>,
Requires<[HasFPARMv8, HasDPVFP]> {
bits<5> Dm;
let Inst{17-16} = rm;
@@ -661,7 +664,8 @@ multiclass vcvt_inst<string opc, bits<2> rm> {
def UD : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0,
(outs SPR:$Sd), (ins DPR:$Dm),
NoItinerary, !strconcat("vcvt", opc, ".u32.f64\t$Sd, $Dm"),
[]>, Requires<[HasFPARMv8, HasDPVFP]> {
[(set SPR:$Sd, (arm_ftoui (f64 (node (f64 DPR:$Dm)))))]>,
Requires<[HasFPARMv8, HasDPVFP]> {
bits<5> Dm;
let Inst{17-16} = rm;
@@ -674,10 +678,10 @@ multiclass vcvt_inst<string opc, bits<2> rm> {
}
}
defm VCVTA : vcvt_inst<"a", 0b00>;
defm VCVTA : vcvt_inst<"a", 0b00, frnd>;
defm VCVTN : vcvt_inst<"n", 0b01>;
defm VCVTP : vcvt_inst<"p", 0b10>;
defm VCVTM : vcvt_inst<"m", 0b11>;
defm VCVTP : vcvt_inst<"p", 0b10, fceil>;
defm VCVTM : vcvt_inst<"m", 0b11, ffloor>;
def VNEGD : ADuI<0b11101, 0b11, 0b0001, 0b01, 0,
(outs DPR:$Dd), (ins DPR:$Dm),