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Fix a bug in the scheduler's handling of "unspillable" vregs.

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Imagine we see:

EFLAGS = inst1
EFLAGS = inst2 FLAGS
gpr = inst3 EFLAGS

Previously, we would refuse to schedule inst2 because it clobbers
the EFLAGS of the predecessor.  However, it also uses the EFLAGS
of the predecessor, so it is safe to emit.  SDep edges ensure that
the right order happens already anyway.

This fixes 2 testsuite crashes with the X86 patch I'm going to
commit next.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122211 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2010-12-20 00:55:43 +00:00
parent e273690d7a
commit 37944985a5
1 changed files with 14 additions and 1 deletions
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15
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
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@ -283,7 +283,7 @@ void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU, unsigned CurCycle) {
Sequence.push_back(SU);
AvailableQueue->ScheduledNode(SU);
ReleasePredecessors(SU, CurCycle);
// Release all the implicit physical register defs that are live.
@ -704,6 +704,19 @@ DelayForLiveRegsBottomUp(SUnit *SU, SmallVector<unsigned, 4> &LRegs) {
}
// Okay, we now know all of the live registers that are defined by an
// immediate predecessor. It is ok to kill these registers if we are also
// using it.
for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
I != E; ++I) {
if (I->isAssignedRegDep() &&
LiveRegCycles[I->getReg()] == I->getSUnit()->getHeight()) {
unsigned Reg = I->getReg();
if (RegAdded.erase(Reg))
LRegs.erase(std::find(LRegs.begin(), LRegs.end(), Reg));
}
}
return !LRegs.empty();
}