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Add patterns for multiply, simplify Y register handling stuff, add RDY instruction

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24796 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-12-17 22:22:53 +00:00
parent 9034b883a4
commit 37949f5c2b
6 changed files with 34 additions and 34 deletions
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23
lib/Target/Sparc/SparcInstrInfo.td
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@ -358,10 +358,12 @@ def UMULri : F3_2<2, 0b001010,
"umul $b, $c, $dst", []>;
def SMULrr : F3_1<2, 0b001011,
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
"smul $b, $c, $dst", []>;
"smul $b, $c, $dst",
[(set IntRegs:$dst, (mul IntRegs:$b, IntRegs:$c))]>;
def SMULri : F3_2<2, 0b001011,
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
"smul $b, $c, $dst", []>;
"smul $b, $c, $dst",
[(set IntRegs:$dst, (mul IntRegs:$b, simm13:$c))]>;
// Section B.19 - Divide Instructions, p. 115
def UDIVrr : F3_1<2, 0b001110,
@ -467,13 +469,18 @@ let Uses = [O0, O1, O2, O3, O4, O5], hasDelaySlot = 1, isCall = 1 in {
"jmpl $b+$c, $dst", []>;
}
// Section B.28 - Read State Register Instructions
def RDY : F3_1<2, 0b101000,
(ops IntRegs:$dst),
"rdy $dst", []>;
// Section B.29 - Write State Register Instructions
def WRrr : F3_1<2, 0b110000,
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
"wr $b, $c, $dst", []>;
def WRri : F3_2<2, 0b110000,
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
"wr $b, $c, $dst", []>;
def WRYrr : F3_1<2, 0b110000,
(ops IntRegs:$b, IntRegs:$c),
"wr $b, $c, %y", []>;
def WRYri : F3_2<2, 0b110000,
(ops IntRegs:$b, i32imm:$c),
"wr $b, $c, %y", []>;
// Convert Integer to Floating-point Instructions, p. 141
def FITOS : F3_3<2, 0b110100, 0b011000100,

7
lib/Target/Sparc/SparcRegisterInfo.td
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@ -30,11 +30,6 @@ class Rd<bits<5> num, string n, list<Register> aliases> : SparcReg<n> {
let Num = num;
let Aliases = aliases;
}
// Rs - Special "ancillary state registers" registers, like the Y, ASR, PSR,
// WIM, TBR, etc registers
class Rs<bits<5> num, string n> : SparcReg<n> {
let Num = num;
}
// Integer registers
def G0 : Ri< 0, "G0">; def G1 : Ri< 1, "G1">; def G2 : Ri< 2, "G2">;
@ -76,8 +71,6 @@ def D10 : Rd<20, "F20", [F20, F21]>; def D11 : Rd<22, "F22", [F22, F23]>;
def D12 : Rd<24, "F24", [F24, F25]>; def D13 : Rd<26, "F26", [F26, F27]>;
def D14 : Rd<28, "F28", [F28, F29]>; def D15 : Rd<30, "F30", [F30, F31]>;
// The Y register.
def Y : Rs<0, "Y">;
// Register classes.
//

4
lib/Target/Sparc/SparcV8ISelSimple.cpp
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@ -1480,11 +1480,11 @@ void V8ISel::visitBinaryOperator (Instruction &I) {
unsigned Tmp = makeAnotherReg (I.getType ());
// Sign extend into the Y register
BuildMI (BB, V8::SRAri, 2, Tmp).addReg (Op0Reg).addZImm (31);
BuildMI (BB, V8::WRrr, 2, V8::Y).addReg (Tmp).addReg (V8::G0);
BuildMI (BB, V8::WRYrr, 2).addReg (Tmp).addReg (V8::G0);
BuildMI (BB, V8::SDIVrr, 2, Dest).addReg (Op0Reg).addReg (Op1Reg);
} else {
// Zero extend into the Y register, ie, just set it to zero
BuildMI (BB, V8::WRrr, 2, V8::Y).addReg (V8::G0).addReg (V8::G0);
BuildMI (BB, V8::WRYrr, 2).addReg (V8::G0).addReg (V8::G0);
BuildMI (BB, V8::UDIVrr, 2, Dest).addReg (Op0Reg).addReg (Op1Reg);
}

4
lib/Target/SparcV8/SparcV8ISelSimple.cpp
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@ -1480,11 +1480,11 @@ void V8ISel::visitBinaryOperator (Instruction &I) {
unsigned Tmp = makeAnotherReg (I.getType ());
// Sign extend into the Y register
BuildMI (BB, V8::SRAri, 2, Tmp).addReg (Op0Reg).addZImm (31);
BuildMI (BB, V8::WRrr, 2, V8::Y).addReg (Tmp).addReg (V8::G0);
BuildMI (BB, V8::WRYrr, 2).addReg (Tmp).addReg (V8::G0);
BuildMI (BB, V8::SDIVrr, 2, Dest).addReg (Op0Reg).addReg (Op1Reg);
} else {
// Zero extend into the Y register, ie, just set it to zero
BuildMI (BB, V8::WRrr, 2, V8::Y).addReg (V8::G0).addReg (V8::G0);
BuildMI (BB, V8::WRYrr, 2).addReg (V8::G0).addReg (V8::G0);
BuildMI (BB, V8::UDIVrr, 2, Dest).addReg (Op0Reg).addReg (Op1Reg);
}

23
lib/Target/SparcV8/SparcV8InstrInfo.td
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@ -358,10 +358,12 @@ def UMULri : F3_2<2, 0b001010,
"umul $b, $c, $dst", []>;
def SMULrr : F3_1<2, 0b001011,
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
"smul $b, $c, $dst", []>;
"smul $b, $c, $dst",
[(set IntRegs:$dst, (mul IntRegs:$b, IntRegs:$c))]>;
def SMULri : F3_2<2, 0b001011,
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
"smul $b, $c, $dst", []>;
"smul $b, $c, $dst",
[(set IntRegs:$dst, (mul IntRegs:$b, simm13:$c))]>;
// Section B.19 - Divide Instructions, p. 115
def UDIVrr : F3_1<2, 0b001110,
@ -467,13 +469,18 @@ let Uses = [O0, O1, O2, O3, O4, O5], hasDelaySlot = 1, isCall = 1 in {
"jmpl $b+$c, $dst", []>;
}
// Section B.28 - Read State Register Instructions
def RDY : F3_1<2, 0b101000,
(ops IntRegs:$dst),
"rdy $dst", []>;
// Section B.29 - Write State Register Instructions
def WRrr : F3_1<2, 0b110000,
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
"wr $b, $c, $dst", []>;
def WRri : F3_2<2, 0b110000,
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
"wr $b, $c, $dst", []>;
def WRYrr : F3_1<2, 0b110000,
(ops IntRegs:$b, IntRegs:$c),
"wr $b, $c, %y", []>;
def WRYri : F3_2<2, 0b110000,
(ops IntRegs:$b, i32imm:$c),
"wr $b, $c, %y", []>;
// Convert Integer to Floating-point Instructions, p. 141
def FITOS : F3_3<2, 0b110100, 0b011000100,

7
lib/Target/SparcV8/SparcV8RegisterInfo.td
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@ -30,11 +30,6 @@ class Rd<bits<5> num, string n, list<Register> aliases> : SparcReg<n> {
let Num = num;
let Aliases = aliases;
}
// Rs - Special "ancillary state registers" registers, like the Y, ASR, PSR,
// WIM, TBR, etc registers
class Rs<bits<5> num, string n> : SparcReg<n> {
let Num = num;
}
// Integer registers
def G0 : Ri< 0, "G0">; def G1 : Ri< 1, "G1">; def G2 : Ri< 2, "G2">;
@ -76,8 +71,6 @@ def D10 : Rd<20, "F20", [F20, F21]>; def D11 : Rd<22, "F22", [F22, F23]>;
def D12 : Rd<24, "F24", [F24, F25]>; def D13 : Rd<26, "F26", [F26, F27]>;
def D14 : Rd<28, "F28", [F28, F29]>; def D15 : Rd<30, "F30", [F30, F31]>;
// The Y register.
def Y : Rs<0, "Y">;
// Register classes.
//