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[AArch64]Fix the problem that can't select mul of v1i64/v2i64 types.

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E.g. Can't select such IR:
     %tmp = mul <2 x i64> %a, %b


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198188 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hao Liu 2013-12-30 01:38:41 +00:00
parent 14eb675218
commit 3796015b5b
2 changed files with 27 additions and 0 deletions
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12
lib/Target/AArch64/AArch64ISelLowering.cpp
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@ -385,6 +385,18 @@ AArch64TargetLowering::AArch64TargetLowering(AArch64TargetMachine &TM)
setTruncStoreAction(VT, VT1, Expand);
}
}
// There is no v1i64/v2i64 multiply, expand v1i64/v2i64 to GPR i64 multiply.
// FIXME: For a v2i64 multiply, we copy VPR to GPR and do 2 i64 multiplies,
// and then copy back to VPR. This solution may be optimized by Following 3
// NEON instructions:
// pmull v2.1q, v0.1d, v1.1d
// pmull2 v3.1q, v0.2d, v1.2d
// ins v2.d[1], v3.d[0]
// As currently we can't verify the correctness of such assumption, we can
// do such optimization in the future.
setOperationAction(ISD::MUL, MVT::v1i64, Expand);
setOperationAction(ISD::MUL, MVT::v2i64, Expand);
}
}

15
test/CodeGen/AArch64/neon-mul-div.ll
View File

@ -37,6 +37,21 @@ define <4 x i32> @mul4x32(<4 x i32> %A, <4 x i32> %B) {
ret <4 x i32> %tmp3
}
define <1 x i64> @mul1xi64(<1 x i64> %A, <1 x i64> %B) {
;CHECK-LABEL: mul1xi64:
;CHECK: mul x{{[0-9]+}}, x{{[0-9]+}}, x{{[0-9]+}}
%tmp3 = mul <1 x i64> %A, %B;
ret <1 x i64> %tmp3
}
define <2 x i64> @mul2xi64(<2 x i64> %A, <2 x i64> %B) {
;CHECK-LABEL: mul2xi64:
;CHECK: mul x{{[0-9]+}}, x{{[0-9]+}}, x{{[0-9]+}}
;CHECK: mul x{{[0-9]+}}, x{{[0-9]+}}, x{{[0-9]+}}
%tmp3 = mul <2 x i64> %A, %B;
ret <2 x i64> %tmp3
}
define <2 x float> @mul2xfloat(<2 x float> %A, <2 x float> %B) {
;CHECK: fmul {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
%tmp3 = fmul <2 x float> %A, %B;