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[AArch64]Fix the problem that can't select mul of v1i64/v2i64 types.
E.g. Can't select such IR: %tmp = mul <2 x i64> %a, %b git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198188 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -385,6 +385,18 @@ AArch64TargetLowering::AArch64TargetLowering(AArch64TargetMachine &TM)
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setTruncStoreAction(VT, VT1, Expand);
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}
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}
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// There is no v1i64/v2i64 multiply, expand v1i64/v2i64 to GPR i64 multiply.
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// FIXME: For a v2i64 multiply, we copy VPR to GPR and do 2 i64 multiplies,
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// and then copy back to VPR. This solution may be optimized by Following 3
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// NEON instructions:
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// pmull v2.1q, v0.1d, v1.1d
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// pmull2 v3.1q, v0.2d, v1.2d
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// ins v2.d[1], v3.d[0]
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// As currently we can't verify the correctness of such assumption, we can
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// do such optimization in the future.
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setOperationAction(ISD::MUL, MVT::v1i64, Expand);
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setOperationAction(ISD::MUL, MVT::v2i64, Expand);
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}
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}
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@ -37,6 +37,21 @@ define <4 x i32> @mul4x32(<4 x i32> %A, <4 x i32> %B) {
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ret <4 x i32> %tmp3
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}
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define <1 x i64> @mul1xi64(<1 x i64> %A, <1 x i64> %B) {
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;CHECK-LABEL: mul1xi64:
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;CHECK: mul x{{[0-9]+}}, x{{[0-9]+}}, x{{[0-9]+}}
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%tmp3 = mul <1 x i64> %A, %B;
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ret <1 x i64> %tmp3
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}
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define <2 x i64> @mul2xi64(<2 x i64> %A, <2 x i64> %B) {
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;CHECK-LABEL: mul2xi64:
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;CHECK: mul x{{[0-9]+}}, x{{[0-9]+}}, x{{[0-9]+}}
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;CHECK: mul x{{[0-9]+}}, x{{[0-9]+}}, x{{[0-9]+}}
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%tmp3 = mul <2 x i64> %A, %B;
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ret <2 x i64> %tmp3
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}
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define <2 x float> @mul2xfloat(<2 x float> %A, <2 x float> %B) {
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;CHECK: fmul {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
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%tmp3 = fmul <2 x float> %A, %B;
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