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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55004 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2008-08-19 20:36:33 +00:00
parent 56e0f87dcc
commit 379cad44ec
1 changed files with 8 additions and 1 deletions
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9
utils/TableGen/FastISelEmitter.cpp
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@ -163,6 +163,9 @@ void FastISelEmitter::run(std::ostream &OS) {
CodeGenInstruction &II = CGP.getTargetInfo().getInstruction(Op->getName());
if (II.OperandList.empty())
continue;
// For now, ignore instructions where the first operand is not an
// output register.
Record *Op0Rec = II.OperandList[0].Rec;
if (!Op0Rec->isSubClassOf("RegisterClass"))
continue;
@ -191,7 +194,7 @@ void FastISelEmitter::run(std::ostream &OS) {
if (!InstPatNode->getPredicateFn().empty())
continue;
// Check all the operands. For now only accept register operands.
// Check all the operands.
OperandsSignature Operands;
for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) {
TreePatternNode *Op = InstPatNode->getChild(i);
@ -204,11 +207,15 @@ void FastISelEmitter::run(std::ostream &OS) {
if (!OpDI)
goto continue_label;
Record *OpLeafRec = OpDI->getDef();
// For now, only accept register operands.
if (!OpLeafRec->isSubClassOf("RegisterClass"))
goto continue_label;
// For now, require the register operands' register classes to all
// be the same.
const CodeGenRegisterClass *RC = &Target.getRegisterClass(OpLeafRec);
if (!RC)
goto continue_label;
// For now, all the operands must have the same type.
if (Op->getTypeNum(0) != VT)
goto continue_label;
Operands.Operands.push_back("r");