From 37e5cfa4aae0dd693ab0c35ff78d37f5ddfe177d Mon Sep 17 00:00:00 2001 From: Stepan Dyatkovskiy Date: Thu, 3 Apr 2014 11:29:15 +0000 Subject: [PATCH] PR19320: The trouble as in ARMAsmParser, in ParseInstruction method. It assumes that ARM::R12 + 1 == ARM::SP. It is wrong, since ARM:: codes are generated by tablegen and actually could be any random numbers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205524 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 13 +++++++++---- test/MC/ARM/ldrd-strd-gnu-sp.s | 9 +++++++++ 2 files changed, 18 insertions(+), 4 deletions(-) create mode 100644 test/MC/ARM/ldrd-strd-gnu-sp.s diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index 8372f05c598..9c57a244fdb 100644 --- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -5408,11 +5408,16 @@ bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name, Operands.size() == 4) { ARMOperand *Op = static_cast(Operands[2]); assert(Op->isReg() && "expected register argument"); - assert(MRI->getMatchingSuperReg(Op->getReg(), ARM::gsub_0, - &MRI->getRegClass(ARM::GPRPairRegClassID)) - && "expected register pair"); + + unsigned SuperReg = MRI->getMatchingSuperReg( + Op->getReg(), ARM::gsub_0, &MRI->getRegClass(ARM::GPRPairRegClassID)); + + assert(SuperReg && "expected register pair"); + + unsigned PairedReg = MRI->getSubReg(SuperReg, ARM::gsub_1); + Operands.insert(Operands.begin() + 3, - ARMOperand::CreateReg(Op->getReg() + 1, Op->getStartLoc(), + ARMOperand::CreateReg(PairedReg, Op->getStartLoc(), Op->getEndLoc())); } diff --git a/test/MC/ARM/ldrd-strd-gnu-sp.s b/test/MC/ARM/ldrd-strd-gnu-sp.s new file mode 100644 index 00000000000..21efae98525 --- /dev/null +++ b/test/MC/ARM/ldrd-strd-gnu-sp.s @@ -0,0 +1,9 @@ +// PR19320 +// RUN: llvm-mc -triple=armv7-linux-gnueabi -show-encoding < %s | FileCheck %s +.text + +// CHECK: ldrd r12, sp, [r0, #32] @ encoding: [0xd0,0xc2,0xc0,0xe1] + ldrd r12, [r0, #32] + +// CHECK: strd r12, sp, [r0, #32] @ encoding: [0xf0,0xc2,0xc0,0xe1] + strd r12, [r0, #32]