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https://github.com/c64scene-ar/llvm-6502.git
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ARM instruction table was modified by adding information to generate multiply instruction of V5TE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41626 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Raul Herbster
parent
d05c04c169
commit
37fb5b154c
@ -342,33 +342,38 @@ class Format<bits<5> val> {
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def Pseudo : Format<1>;
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def MulFrm : Format<2>;
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def Branch : Format<3>;
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def BranchMisc : Format<4>;
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def MulSMLAW : Format<3>;
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def MulSMULW : Format<4>;
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def MulSMLA : Format<5>;
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def MulSMUL : Format<6>;
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def Branch : Format<7>;
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def BranchMisc : Format<8>;
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def DPRdIm : Format<5>;
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def DPRdReg : Format<6>;
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def DPRdSoReg : Format<7>;
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def DPRdMisc : Format<8>;
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def DPRnIm : Format<9>;
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def DPRnReg : Format<10>;
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def DPRnSoReg : Format<11>;
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def DPRIm : Format<12>;
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def DPRReg : Format<13>;
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def DPRSoReg : Format<14>;
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def DPRImS : Format<15>;
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def DPRRegS : Format<16>;
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def DPRSoRegS : Format<17>;
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def DPRdIm : Format<9>;
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def DPRdReg : Format<10>;
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def DPRdSoReg : Format<11>;
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def DPRdMisc : Format<12>;
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def DPRnIm : Format<13>;
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def DPRnReg : Format<14>;
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def DPRnSoReg : Format<15>;
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def DPRIm : Format<16>;
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def DPRReg : Format<17>;
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def DPRSoReg : Format<18>;
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def DPRImS : Format<19>;
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def DPRRegS : Format<20>;
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def DPRSoRegS : Format<21>;
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def LdFrm : Format<18>;
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def StFrm : Format<19>;
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def LdFrm : Format<22>;
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def StFrm : Format<23>;
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def ArithMisc : Format<20>;
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def ThumbFrm : Format<21>;
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def VFPFrm : Format<22>;
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def ArithMisc : Format<24>;
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def ThumbFrm : Format<25>;
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def VFPFrm : Format<26>;
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//===----------------------------------------------------------------------===//
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// ARM Instruction templates.
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//
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@ -776,7 +781,7 @@ let isBranch = 1, isTerminator = 1 in {
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// FIXME: should be able to write a pattern for ARMBrcond, but can't use
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// a two-value operand where a dag node expects two operands. :(
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def Bcc : AI<0x0, (outs), (ins brtarget:$target), Branch,
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def Bcc : AI<0xA, (outs), (ins brtarget:$target), Branch,
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"b", " $target",
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[/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>;
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}
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@ -815,7 +820,7 @@ def LDRSB : AI3<0xD, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm,
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[(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
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// Load doubleword
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def LDRD : AI3<0x0, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm,
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def LDRD : AI3<0xD, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm,
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"ldr", "d $dst, $addr",
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[]>, Requires<[IsARM, HasV5T]>;
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@ -877,7 +882,7 @@ def STRB : AI2<0x1, (outs), (ins GPR:$src, addrmode2:$addr), StFrm,
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[(truncstorei8 GPR:$src, addrmode2:$addr)]>;
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// Store doubleword
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def STRD : AI3<0x0, (outs), (ins GPR:$src, addrmode3:$addr), StFrm,
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def STRD : AI3<0xF, (outs), (ins GPR:$src, addrmode3:$addr), StFrm,
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"str", "d $src, $addr",
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[]>, Requires<[IsARM, HasV5T]>;
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@ -1125,76 +1130,86 @@ def SMMLS : AI<0x0, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), MulFrm,
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[(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>,
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Requires<[IsARM, HasV6]>;
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multiclass AI_smul<bits<4> opcod, string opc, PatFrag opnode> {
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def BB : AI<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulFrm,
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multiclass AI_smul<string opc, PatFrag opnode> {
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def BB : AI<0x8, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMUL,
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!strconcat(opc, "bb"), " $dst, $a, $b",
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[(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
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(sext_inreg GPR:$b, i16)))]>,
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Requires<[IsARM, HasV5TE]>;
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def BT : AI<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulFrm,
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def BT : AI<0xC, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMUL,
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!strconcat(opc, "bt"), " $dst, $a, $b",
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[(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
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(sra GPR:$b, 16)))]>,
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Requires<[IsARM, HasV5TE]>;
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def TB : AI<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulFrm,
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def TB : AI<0xA, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMUL,
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!strconcat(opc, "tb"), " $dst, $a, $b",
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[(set GPR:$dst, (opnode (sra GPR:$a, 16),
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(sext_inreg GPR:$b, i16)))]>,
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Requires<[IsARM, HasV5TE]>;
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def TT : AI<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulFrm,
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def TT : AI<0xE, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMUL,
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!strconcat(opc, "tt"), " $dst, $a, $b",
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[(set GPR:$dst, (opnode (sra GPR:$a, 16),
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(sra GPR:$b, 16)))]>,
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Requires<[IsARM, HasV5TE]>;
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def WB : AI<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulFrm,
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def WB : AI<0xA, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMULW,
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!strconcat(opc, "wb"), " $dst, $a, $b",
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[(set GPR:$dst, (sra (opnode GPR:$a,
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(sext_inreg GPR:$b, i16)), 16))]>,
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Requires<[IsARM, HasV5TE]>;
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def WT : AI<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulFrm,
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def WT : AI<0xE, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMULW,
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!strconcat(opc, "wt"), " $dst, $a, $b",
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[(set GPR:$dst, (sra (opnode GPR:$a,
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(sra GPR:$b, 16)), 16))]>,
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Requires<[IsARM, HasV5TE]>;
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}
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multiclass AI_smla<bits<4> opcod, string opc, PatFrag opnode> {
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def BB : AI<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulFrm,
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multiclass AI_smla<string opc, PatFrag opnode> {
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def BB : AI<0x8, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLA,
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!strconcat(opc, "bb"), " $dst, $a, $b, $acc",
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[(set GPR:$dst, (add GPR:$acc,
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(opnode (sext_inreg GPR:$a, i16),
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(sext_inreg GPR:$b, i16))))]>,
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Requires<[IsARM, HasV5TE]>;
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def BT : AI<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulFrm,
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def BT : AI<0xC, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLA,
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!strconcat(opc, "bt"), " $dst, $a, $b, $acc",
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[(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
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(sra GPR:$b, 16))))]>,
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Requires<[IsARM, HasV5TE]>;
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def TB : AI<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulFrm,
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def TB : AI<0xA, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLA,
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!strconcat(opc, "tb"), " $dst, $a, $b, $acc",
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[(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, 16),
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(sext_inreg GPR:$b, i16))))]>,
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Requires<[IsARM, HasV5TE]>;
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def TT : AI<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulFrm,
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def TT : AI<0xE, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLA,
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!strconcat(opc, "tt"), " $dst, $a, $b, $acc",
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[(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, 16),
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(sra GPR:$b, 16))))]>,
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Requires<[IsARM, HasV5TE]>;
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def WB : AI<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulFrm,
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def WB : AI<0xA, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLAW,
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!strconcat(opc, "wb"), " $dst, $a, $b, $acc",
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[(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
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(sext_inreg GPR:$b, i16)), 16)))]>,
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Requires<[IsARM, HasV5TE]>;
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def WT : AI<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulFrm,
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def WT : AI<0xE, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLAW,
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!strconcat(opc, "wt"), " $dst, $a, $b, $acc",
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[(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
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(sra GPR:$b, 16)), 16)))]>,
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Requires<[IsARM, HasV5TE]>;
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}
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defm SMUL : AI_smul<0x0, "smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
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defm SMLA : AI_smla<0x0, "smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
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defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
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defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
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// TODO: Halfword multiple accumulate long: SMLAL<x><y>
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// TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
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