diff --git a/lib/Target/ARM64/ARM64ISelLowering.cpp b/lib/Target/ARM64/ARM64ISelLowering.cpp
index b6672ee0d7f..66207790c8a 100644
--- a/lib/Target/ARM64/ARM64ISelLowering.cpp
+++ b/lib/Target/ARM64/ARM64ISelLowering.cpp
@@ -5615,7 +5615,7 @@ SDValue ARM64TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
   }
   MachineSDNode *N =
       DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, SDLoc(Op),
-                         Op.getValueType(), DAG.getUNDEF(Op0.getValueType()),
+                         Op.getValueType(), DAG.getUNDEF(Op.getValueType()),
                          Op0, DAG.getTargetConstant(SubIdx, MVT::i32));
   return SDValue(N, 0);
 }
diff --git a/test/CodeGen/ARM64/simd-scalar-to-vector.ll b/test/CodeGen/ARM64/simd-scalar-to-vector.ll
index fe0c6fedddb..6c0b840a5c1 100644
--- a/test/CodeGen/ARM64/simd-scalar-to-vector.ll
+++ b/test/CodeGen/ARM64/simd-scalar-to-vector.ll
@@ -1,10 +1,15 @@
 ; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
+; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple -O0 | FileCheck %s --check-prefix=CHECK-FAST
 
 define <16 x i8> @foo(<16 x i8> %a) nounwind optsize readnone ssp {
-; CHECK: uaddlv.16b	h0, v0
-; CHECK: rshrn.8b	v0, v0, #4
-; CHECK: dup.16b	v0, v0[0]
+; CHECK: uaddlv.16b h0, v0
+; CHECK: rshrn.8b v0, v0, #4
+; CHECK: dup.16b v0, v0[0]
 ; CHECK: ret
+
+; CHECK-FAST: uaddlv.16b
+; CHECK-FAST: rshrn.8b
+; CHECK-FAST: dup.16b
   %tmp = tail call i32 @llvm.arm64.neon.uaddlv.i32.v16i8(<16 x i8> %a) nounwind
   %tmp1 = trunc i32 %tmp to i16
   %tmp2 = insertelement <8 x i16> undef, i16 %tmp1, i32 0