From 38466309d5c8ce408f05567fa47aeaa3b5826080 Mon Sep 17 00:00:00 2001
From: Jim Grosbach <grosbach@apple.com>
Date: Fri, 19 Aug 2011 18:55:51 +0000
Subject: [PATCH] Thumb assembly parsing and encoding for LDRH.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138060 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/ARM/ARMInstrThumb.td           |  2 ++
 lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 16 ++++++++++++++++
 test/MC/ARM/basic-thumb-instructions.s    | 20 ++++++++++++++++++++
 3 files changed, 38 insertions(+)

diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td
index 35a745aa78a..edc4660034f 100644
--- a/lib/Target/ARM/ARMInstrThumb.td
+++ b/lib/Target/ARM/ARMInstrThumb.td
@@ -169,11 +169,13 @@ def t_addrmode_is4 : Operand<i32>,
 
 // t_addrmode_is2 := reg + imm5 * 2
 //
+def t_addrmode_is2_asm_operand : AsmOperandClass { let Name = "MemThumbRIs2"; }
 def t_addrmode_is2 : Operand<i32>,
                      ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> {
   let EncoderMethod = "getAddrModeISOpValue";
   let DecoderMethod = "DecodeThumbAddrModeIS";
   let PrintMethod = "printThumbAddrModeImm5S2Operand";
+  let ParserMatchClass = t_addrmode_is2_asm_operand;
   let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
 }
 
diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index d04b9b73cc4..60f16f83625 100644
--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -628,6 +628,15 @@ public:
     int64_t Val = Mem.OffsetImm->getValue();
     return Val >= 0 && Val <= 124 && (Val % 4) == 0;
   }
+  bool isMemThumbRIs2() const {
+    if (Kind != Memory || Mem.OffsetRegNum != 0 ||
+        !isARMLowRegister(Mem.BaseRegNum))
+      return false;
+    // Immediate offset, multiple of 4 in range [0, 62].
+    if (!Mem.OffsetImm) return true;
+    int64_t Val = Mem.OffsetImm->getValue();
+    return Val >= 0 && Val <= 62 && (Val % 2) == 0;
+  }
   bool isMemThumbRIs1() const {
     if (Kind != Memory || Mem.OffsetRegNum != 0 ||
         !isARMLowRegister(Mem.BaseRegNum))
@@ -1009,6 +1018,13 @@ public:
     Inst.addOperand(MCOperand::CreateImm(Val));
   }
 
+  void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
+    assert(N == 2 && "Invalid number of operands!");
+    int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 2) : 0;
+    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
+    Inst.addOperand(MCOperand::CreateImm(Val));
+  }
+
   void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
     assert(N == 2 && "Invalid number of operands!");
     int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue()) : 0;
diff --git a/test/MC/ARM/basic-thumb-instructions.s b/test/MC/ARM/basic-thumb-instructions.s
index 4a45820b88a..591c6c6dd0b 100644
--- a/test/MC/ARM/basic-thumb-instructions.s
+++ b/test/MC/ARM/basic-thumb-instructions.s
@@ -230,3 +230,23 @@ _func:
         ldrb r6, [r4, r5]
 
 @ CHECK: ldrb	r6, [r4, r5]            @ encoding: [0x66,0x5d]
+
+
+@------------------------------------------------------------------------------
+@ LDRH (immediate)
+@------------------------------------------------------------------------------
+        ldrh r3, [r3]
+        ldrh r4, [r6, #2]
+        ldrh r5, [r7, #62]
+
+@ CHECK: ldrh	r3, [r3]                @ encoding: [0x1b,0x88]
+@ CHECK: ldrh	r4, [r6, #2]            @ encoding: [0x74,0x88]
+@ CHECK: ldrh	r5, [r7, #62]           @ encoding: [0xfd,0x8f]
+
+
+@------------------------------------------------------------------------------
+@ LDRH (register)
+@------------------------------------------------------------------------------
+        ldrh r6, [r2, r6]
+
+@ CHECK: ldrh	r6, [r2, r6]            @ encoding: [0x96,0x5b]