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ArrayRefize some code. No functionality change.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176648 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Benjamin Kramer 2013-03-07 20:33:29 +00:00
parent a4dd8d6732
commit 3853f74aba
7 changed files with 31 additions and 43 deletions
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4
include/llvm/CodeGen/SelectionDAG.h
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@ -567,7 +567,7 @@ public:
SDValue getNode(unsigned Opcode, DebugLoc DL, EVT VT,
const SDValue *Ops, unsigned NumOps);
SDValue getNode(unsigned Opcode, DebugLoc DL,
const std::vector<EVT> &ResultTys,
ArrayRef<EVT> ResultTys,
const SDValue *Ops, unsigned NumOps);
SDValue getNode(unsigned Opcode, DebugLoc DL, const EVT *VTs, unsigned NumVTs,
const SDValue *Ops, unsigned NumOps);
@ -831,7 +831,7 @@ public:
MachineSDNode *getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2,
EVT VT3, EVT VT4, const SDValue *Ops, unsigned NumOps);
MachineSDNode *getMachineNode(unsigned Opcode, DebugLoc dl,
const std::vector<EVT> &ResultTys, const SDValue *Ops,
ArrayRef<EVT> ResultTys, const SDValue *Ops,
unsigned NumOps);
MachineSDNode *getMachineNode(unsigned Opcode, DebugLoc dl, SDVTList VTs,
const SDValue *Ops, unsigned NumOps);

4
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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@ -4704,7 +4704,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, EVT VT,
}
SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
const std::vector<EVT> &ResultTys,
ArrayRef<EVT> ResultTys,
const SDValue *Ops, unsigned NumOps) {
return getNode(Opcode, DL, getVTList(&ResultTys[0], ResultTys.size()),
Ops, NumOps);
@ -5356,7 +5356,7 @@ SelectionDAG::getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1,
MachineSDNode *
SelectionDAG::getMachineNode(unsigned Opcode, DebugLoc dl,
const std::vector<EVT> &ResultTys,
ArrayRef<EVT> ResultTys,
const SDValue *Ops, unsigned NumOps) {
SDVTList VTs = getVTList(&ResultTys[0], ResultTys.size());
return getMachineNode(Opcode, dl, VTs, Ops, NumOps);

4
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
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@ -1671,9 +1671,7 @@ SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
std::vector<SDValue> Ops(N->op_begin(), N->op_end());
SelectInlineAsmMemoryOperands(Ops);
std::vector<EVT> VTs;
VTs.push_back(MVT::Other);
VTs.push_back(MVT::Glue);
EVT VTs[] = { MVT::Other, MVT::Glue };
SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
VTs, &Ops[0], Ops.size());
New->setNodeId(-1);

4
lib/Target/ARM/ARMISelDAGToDAG.cpp
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@ -3195,9 +3195,7 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
// Store exclusive double return a i32 value which is the return status
// of the issued store.
std::vector<EVT> ResTys;
ResTys.push_back(MVT::i32);
ResTys.push_back(MVT::Other);
EVT ResTys[] = { MVT::i32, MVT::Other };
bool isThumb = Subtarget->isThumb() && Subtarget->hasThumb2();
// Place arguments in the right order.

34
lib/Target/NVPTX/NVPTXISelLowering.cpp
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@ -716,16 +716,15 @@ NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
for (unsigned i=0,e=Ins.size(); i!=e; ++i) {
unsigned sz = Ins[i].VT.getSizeInBits();
if (Ins[i].VT.isInteger() && (sz < 8)) sz = 8;
std::vector<EVT> LoadRetVTs;
LoadRetVTs.push_back(Ins[i].VT);
LoadRetVTs.push_back(MVT::Other); LoadRetVTs.push_back(MVT::Glue);
std::vector<SDValue> LoadRetOps;
LoadRetOps.push_back(Chain);
LoadRetOps.push_back(DAG.getConstant(1, MVT::i32));
LoadRetOps.push_back(DAG.getConstant(resoffset, MVT::i32));
LoadRetOps.push_back(InFlag);
EVT LoadRetVTs[] = { Ins[i].VT, MVT::Other, MVT::Glue };
SDValue LoadRetOps[] = {
Chain,
DAG.getConstant(1, MVT::i32),
DAG.getConstant(resoffset, MVT::i32),
InFlag
};
SDValue retval = DAG.getNode(NVPTXISD::LoadParam, dl, LoadRetVTs,
&LoadRetOps[0], LoadRetOps.size());
LoadRetOps, array_lengthof(LoadRetOps));
Chain = retval.getValue(1);
InFlag = retval.getValue(2);
InVals.push_back(retval);
@ -750,16 +749,15 @@ NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
}
std::vector<SDValue> tempRetVals;
for (unsigned j=0; j<numelems; ++j) {
std::vector<EVT> MoveRetVTs;
MoveRetVTs.push_back(elemtype);
MoveRetVTs.push_back(MVT::Other); MoveRetVTs.push_back(MVT::Glue);
std::vector<SDValue> MoveRetOps;
MoveRetOps.push_back(Chain);
MoveRetOps.push_back(DAG.getConstant(0, MVT::i32));
MoveRetOps.push_back(DAG.getConstant(paramNum, MVT::i32));
MoveRetOps.push_back(InFlag);
EVT MoveRetVTs[] = { elemtype, MVT::Other, MVT::Glue };
SDValue MoveRetOps[] = {
Chain,
DAG.getConstant(0, MVT::i32),
DAG.getConstant(paramNum, MVT::i32),
InFlag
};
SDValue retval = DAG.getNode(NVPTXISD::LoadParam, dl, MoveRetVTs,
&MoveRetOps[0], MoveRetOps.size());
MoveRetOps, array_lengthof(MoveRetOps));
Chain = retval.getValue(1);
InFlag = retval.getValue(2);
tempRetVals.push_back(retval);

15
lib/Target/PowerPC/PPCISelLowering.cpp
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@ -4786,12 +4786,13 @@ SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
MachineFunction &MF = DAG.getMachineFunction();
EVT VT = Op.getValueType();
EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
std::vector<EVT> NodeTys;
SDValue MFFSreg, InFlag;
// Save FP Control Word to register
NodeTys.push_back(MVT::f64); // return register
NodeTys.push_back(MVT::Glue); // unused in this context
EVT NodeTys[] = {
MVT::f64, // return register
MVT::Glue // unused in this context
};
SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
// Save FP register to stack slot
@ -5408,9 +5409,7 @@ SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
Op.getOperand(3), // RHS
DAG.getConstant(CompareOpc, MVT::i32)
};
std::vector<EVT> VTs;
VTs.push_back(Op.getOperand(2).getValueType());
VTs.push_back(MVT::Glue);
EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
// Now that we have the comparison, emit a copy from the CR to a GPR.
@ -6466,14 +6465,12 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
// Create the PPCISD altivec 'dot' comparison node.
std::vector<EVT> VTs;
SDValue Ops[] = {
LHS.getOperand(2), // LHS of compare
LHS.getOperand(3), // RHS of compare
DAG.getConstant(CompareOpc, MVT::i32)
};
VTs.push_back(LHS.getOperand(2).getValueType());
VTs.push_back(MVT::Glue);
EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
// Unpack the result based on how the target uses it.

9
lib/Target/Sparc/SparcISelLowering.cpp
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@ -955,9 +955,7 @@ static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
// Get the condition flag.
SDValue CompareFlag;
if (LHS.getValueType() == MVT::i32) {
std::vector<EVT> VTs;
VTs.push_back(MVT::i32);
VTs.push_back(MVT::Glue);
EVT VTs[] = { MVT::i32, MVT::Glue };
SDValue Ops[2] = { LHS, RHS };
CompareFlag = DAG.getNode(SPISD::CMPICC, dl, VTs, Ops, 2).getValue(1);
if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
@ -986,9 +984,8 @@ static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
SDValue CompareFlag;
if (LHS.getValueType() == MVT::i32) {
std::vector<EVT> VTs;
VTs.push_back(LHS.getValueType()); // subcc returns a value
VTs.push_back(MVT::Glue);
// subcc returns a value
EVT VTs[] = { LHS.getValueType(), MVT::Glue };
SDValue Ops[2] = { LHS, RHS };
CompareFlag = DAG.getNode(SPISD::CMPICC, dl, VTs, Ops, 2).getValue(1);
Opc = SPISD::SELECT_ICC;