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https://github.com/c64scene-ar/llvm-6502.git
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More ARM multiply instuction binary encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117121 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
parent
76f920d316
commit
3870b750e6
@ -934,15 +934,42 @@ class AMul2Ia<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
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}
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// SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y>
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class AMulxyI<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
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class AMulxyIbase<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
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InstrItinClass itin, string opc, string asm, list<dag> pattern>
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: I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
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opc, asm, "", pattern> {
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bits<4> Rn;
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bits<4> Rm;
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let Inst{4} = 0;
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let Inst{7} = 1;
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let Inst{20} = 0;
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let Inst{27-21} = opcod;
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let Inst{6-5} = bit6_5;
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let Inst{11-8} = Rm;
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let Inst{3-0} = Rn;
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}
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class AMulxyI<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
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InstrItinClass itin, string opc, string asm, list<dag> pattern>
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: AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
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bits<4> Rd;
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let Inst{19-16} = Rd;
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}
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// AMulxyI with Ra operand
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class AMulxyIa<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
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InstrItinClass itin, string opc, string asm, list<dag> pattern>
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: AMulxyI<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
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bits<4> Ra;
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let Inst{15-12} = Ra;
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}
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// SMLAL*
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class AMulxyI64<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
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InstrItinClass itin, string opc, string asm, list<dag> pattern>
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: AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
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bits<4> RdLo;
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bits<4> RdHi;
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let Inst{19-16} = RdHi;
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let Inst{15-12} = RdLo;
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}
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// Extend instructions.
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@ -2372,132 +2372,116 @@ def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
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Requires<[IsARM, HasV6]>;
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multiclass AI_smul<string opc, PatFrag opnode> {
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def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
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IIC_iMUL16, !strconcat(opc, "bb"), "\t$dst, $a, $b",
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[(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
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(sext_inreg GPR:$b, i16)))]>,
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Requires<[IsARM, HasV5TE]> {
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}
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def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
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IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
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[(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
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(sext_inreg GPR:$Rm, i16)))]>,
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Requires<[IsARM, HasV5TE]>;
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def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
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IIC_iMUL16, !strconcat(opc, "bt"), "\t$dst, $a, $b",
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[(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
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(sra GPR:$b, (i32 16))))]>,
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Requires<[IsARM, HasV5TE]> {
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}
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def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
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IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
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[(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
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(sra GPR:$Rm, (i32 16))))]>,
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Requires<[IsARM, HasV5TE]>;
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def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
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IIC_iMUL16, !strconcat(opc, "tb"), "\t$dst, $a, $b",
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[(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
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(sext_inreg GPR:$b, i16)))]>,
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Requires<[IsARM, HasV5TE]> {
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}
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def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
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IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
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[(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
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(sext_inreg GPR:$Rm, i16)))]>,
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Requires<[IsARM, HasV5TE]>;
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def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
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IIC_iMUL16, !strconcat(opc, "tt"), "\t$dst, $a, $b",
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[(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
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(sra GPR:$b, (i32 16))))]>,
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Requires<[IsARM, HasV5TE]> {
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}
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def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
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IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
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[(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
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(sra GPR:$Rm, (i32 16))))]>,
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Requires<[IsARM, HasV5TE]>;
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def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
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IIC_iMUL16, !strconcat(opc, "wb"), "\t$dst, $a, $b",
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[(set GPR:$dst, (sra (opnode GPR:$a,
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(sext_inreg GPR:$b, i16)), (i32 16)))]>,
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Requires<[IsARM, HasV5TE]> {
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}
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def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
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IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
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[(set GPR:$Rd, (sra (opnode GPR:$Rn,
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(sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
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Requires<[IsARM, HasV5TE]>;
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def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
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IIC_iMUL16, !strconcat(opc, "wt"), "\t$dst, $a, $b",
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[(set GPR:$dst, (sra (opnode GPR:$a,
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(sra GPR:$b, (i32 16))), (i32 16)))]>,
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Requires<[IsARM, HasV5TE]> {
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}
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def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
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IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
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[(set GPR:$Rd, (sra (opnode GPR:$Rn,
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(sra GPR:$Rm, (i32 16))), (i32 16)))]>,
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Requires<[IsARM, HasV5TE]>;
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}
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multiclass AI_smla<string opc, PatFrag opnode> {
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def BB : AMulxyI<0b0001000, 0b00, (outs GPR:$dst),
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(ins GPR:$a, GPR:$b, GPR:$acc),
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IIC_iMAC16, !strconcat(opc, "bb"), "\t$dst, $a, $b, $acc",
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[(set GPR:$dst, (add GPR:$acc,
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(opnode (sext_inreg GPR:$a, i16),
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(sext_inreg GPR:$b, i16))))]>,
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Requires<[IsARM, HasV5TE]> {
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}
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def BB : AMulxyI<0b0001000, 0b00, (outs GPR:$Rd),
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(ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
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IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
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[(set GPR:$Rd, (add GPR:$Ra,
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(opnode (sext_inreg GPR:$Rn, i16),
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(sext_inreg GPR:$Rm, i16))))]>,
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Requires<[IsARM, HasV5TE]>;
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def BT : AMulxyI<0b0001000, 0b10, (outs GPR:$dst),
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(ins GPR:$a, GPR:$b, GPR:$acc),
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IIC_iMAC16, !strconcat(opc, "bt"), "\t$dst, $a, $b, $acc",
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[(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
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(sra GPR:$b, (i32 16)))))]>,
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Requires<[IsARM, HasV5TE]> {
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}
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def BT : AMulxyI<0b0001000, 0b10, (outs GPR:$Rd),
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(ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
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IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
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[(set GPR:$Rd, (add GPR:$Ra, (opnode (sext_inreg GPR:$Rn, i16),
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(sra GPR:$Rm, (i32 16)))))]>,
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Requires<[IsARM, HasV5TE]>;
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def TB : AMulxyI<0b0001000, 0b01, (outs GPR:$dst),
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(ins GPR:$a, GPR:$b, GPR:$acc),
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IIC_iMAC16, !strconcat(opc, "tb"), "\t$dst, $a, $b, $acc",
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[(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
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(sext_inreg GPR:$b, i16))))]>,
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Requires<[IsARM, HasV5TE]> {
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}
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def TB : AMulxyI<0b0001000, 0b01, (outs GPR:$Rd),
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(ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
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IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
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[(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
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(sext_inreg GPR:$Rm, i16))))]>,
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Requires<[IsARM, HasV5TE]>;
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def TT : AMulxyI<0b0001000, 0b11, (outs GPR:$dst),
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(ins GPR:$a, GPR:$b, GPR:$acc),
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IIC_iMAC16, !strconcat(opc, "tt"), "\t$dst, $a, $b, $acc",
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[(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
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(sra GPR:$b, (i32 16)))))]>,
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Requires<[IsARM, HasV5TE]> {
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}
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def TT : AMulxyI<0b0001000, 0b11, (outs GPR:$Rd),
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(ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
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IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
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[(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
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(sra GPR:$Rm, (i32 16)))))]>,
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Requires<[IsARM, HasV5TE]>;
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def WB : AMulxyI<0b0001001, 0b00, (outs GPR:$dst),
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(ins GPR:$a, GPR:$b, GPR:$acc),
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IIC_iMAC16, !strconcat(opc, "wb"), "\t$dst, $a, $b, $acc",
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[(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
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(sext_inreg GPR:$b, i16)), (i32 16))))]>,
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Requires<[IsARM, HasV5TE]> {
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}
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def WB : AMulxyI<0b0001001, 0b00, (outs GPR:$Rd),
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(ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
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IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
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[(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
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(sext_inreg GPR:$Rm, i16)), (i32 16))))]>,
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Requires<[IsARM, HasV5TE]>;
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def WT : AMulxyI<0b0001001, 0b10, (outs GPR:$dst),
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(ins GPR:$a, GPR:$b, GPR:$acc),
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IIC_iMAC16, !strconcat(opc, "wt"), "\t$dst, $a, $b, $acc",
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[(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
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(sra GPR:$b, (i32 16))), (i32 16))))]>,
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Requires<[IsARM, HasV5TE]> {
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}
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def WT : AMulxyI<0b0001001, 0b10, (outs GPR:$Rd),
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(ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
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IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
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[(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
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(sra GPR:$Rm, (i32 16))), (i32 16))))]>,
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Requires<[IsARM, HasV5TE]>;
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}
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defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
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defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
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// Halfword multiply accumulate long: SMLAL<x><y> -- for disassembly only
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def SMLALBB : AMulxyI<0b0001010, 0b00, (outs GPR:$ldst, GPR:$hdst),
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(ins GPR:$a, GPR:$b),
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IIC_iMAC64, "smlalbb", "\t$ldst, $hdst, $a, $b",
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def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPR:$RdLo, GPR:$RdHi),
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(ins GPR:$Rn, GPR:$Rm),
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IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm",
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[/* For disassembly only; pattern left blank */]>,
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Requires<[IsARM, HasV5TE]> {
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}
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Requires<[IsARM, HasV5TE]>;
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def SMLALBT : AMulxyI<0b0001010, 0b10, (outs GPR:$ldst, GPR:$hdst),
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(ins GPR:$a, GPR:$b),
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IIC_iMAC64, "smlalbt", "\t$ldst, $hdst, $a, $b",
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def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPR:$RdLo, GPR:$RdHi),
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(ins GPR:$Rn, GPR:$Rm),
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IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm",
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[/* For disassembly only; pattern left blank */]>,
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Requires<[IsARM, HasV5TE]> {
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}
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Requires<[IsARM, HasV5TE]>;
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def SMLALTB : AMulxyI<0b0001010, 0b01, (outs GPR:$ldst, GPR:$hdst),
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(ins GPR:$a, GPR:$b),
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IIC_iMAC64, "smlaltb", "\t$ldst, $hdst, $a, $b",
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def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPR:$RdLo, GPR:$RdHi),
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(ins GPR:$Rn, GPR:$Rm),
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IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm",
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[/* For disassembly only; pattern left blank */]>,
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Requires<[IsARM, HasV5TE]> {
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}
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Requires<[IsARM, HasV5TE]>;
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def SMLALTT : AMulxyI<0b0001010, 0b11, (outs GPR:$ldst, GPR:$hdst),
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(ins GPR:$a, GPR:$b),
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IIC_iMAC64, "smlaltt", "\t$ldst, $hdst, $a, $b",
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def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPR:$RdLo, GPR:$RdHi),
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(ins GPR:$Rn, GPR:$Rm),
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IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm",
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[/* For disassembly only; pattern left blank */]>,
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Requires<[IsARM, HasV5TE]> {
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}
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Requires<[IsARM, HasV5TE]>;
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// Helper class for AI_smld -- for disassembly only
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class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
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@ -150,4 +150,34 @@ define i32 @f15(i32 %x, i32 %y) {
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%tmp3.upgrd.2 = trunc i64 %tmp3 to i32
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ret i32 %tmp3.upgrd.2
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}
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define i32 @f16(i16 %x, i32 %y) {
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; CHECK: f16:
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; CHECK: smulbt r0, r0, r1 @ encoding: [0xc0,0x01,0x60,0xe1]
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%tmp1 = add i16 %x, 2
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%tmp2 = sext i16 %tmp1 to i32
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%tmp3 = ashr i32 %y, 16
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%tmp4 = mul i32 %tmp2, %tmp3
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ret i32 %tmp4
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}
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define i32 @f17(i32 %x, i32 %y) {
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; CHECK: f17:
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; CHECK: smultt r0, r1, r0 @ encoding: [0xe1,0x00,0x60,0xe1]
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%tmp1 = ashr i32 %x, 16
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%tmp3 = ashr i32 %y, 16
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%tmp4 = mul i32 %tmp3, %tmp1
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ret i32 %tmp4
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}
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define i32 @f18(i32 %a, i16 %x, i32 %y) {
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; CHECK: f18:
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; CHECK: smlabt r0, r1, r2, r0 @ encoding: [0xc1,0x02,0x00,0xe1]
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%tmp = sext i16 %x to i32
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%tmp2 = ashr i32 %y, 16
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%tmp3 = mul i32 %tmp2, %tmp
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%tmp5 = add i32 %tmp3, %a
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ret i32 %tmp5
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}
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declare void @llvm.trap() nounwind
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