6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-07-25 13:24:46 +00:00
Code Issues Projects Releases Wiki Activity

Move the Thumb2 SSAT and USAT optional shift operator out of the

Browse Source 
instruction opcode.  This fixes part of PR7792.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111047 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson
2010-08-13 21:48:10 +00:00
parent 0ad2c7ace8
commit 38aa2871fc
3 changed files with 25 additions and 39 deletions
Download Patch File Download Diff File Expand all files Collapse all files

22
lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
View File

@@ -1462,8 +1462,8 @@ static bool DisassembleThumb2DPModImm(MCInst &MI, unsigned Opcode,
static inline bool Thumb2SaturateOpcode(unsigned Opcode) {
switch (Opcode) {
case ARM::t2SSATlsl: case ARM::t2SSATasr: case ARM::t2SSAT16:
case ARM::t2USATlsl: case ARM::t2USATasr: case ARM::t2USAT16:
case ARM::t2SSAT: case ARM::t2SSAT16:
case ARM::t2USAT: case ARM::t2USAT16:
return true;
default:
return false;
@@ -1471,7 +1471,7 @@ static inline bool Thumb2SaturateOpcode(unsigned Opcode) {
}
/// DisassembleThumb2Sat - Disassemble Thumb2 saturate instructions:
/// o t2SSAT[lsl|asr], t2USAT[lsl|asr]: Rs sat_pos Rn shamt
/// o t2SSAT, t2USAT: Rs sat_pos Rn shamt
/// o t2SSAT16, t2USAT16: Rs sat_pos Rn
static bool DisassembleThumb2Sat(MCInst &MI, unsigned Opcode, uint32_t insn,
unsigned &NumOpsAdded, BO B) {
@@ -1483,9 +1483,7 @@ static bool DisassembleThumb2Sat(MCInst &MI, unsigned Opcode, uint32_t insn,
decodeRs(insn))));
unsigned Pos = slice(insn, 4, 0);
if (Opcode == ARM::t2SSATlsl ||
Opcode == ARM::t2SSATasr ||
Opcode == ARM::t2SSAT16)
if (Opcode == ARM::t2SSAT || Opcode == ARM::t2SSAT16)
Pos += 1;
MI.addOperand(MCOperand::CreateImm(Pos));
@@ -1493,11 +1491,17 @@ static bool DisassembleThumb2Sat(MCInst &MI, unsigned Opcode, uint32_t insn,
decodeRn(insn))));
if (NumOpsAdded == 4) {
ARM_AM::ShiftOpc Opc = (slice(insn, 21, 21) != 0 ?
ARM_AM::asr : ARM_AM::lsl);
// Inst{14-12:7-6} encodes the imm5 shift amount.
unsigned ShAmt = slice(insn, 14, 12) << 2 | slice(insn, 7, 6);
if ((Opcode == ARM::t2SSATasr || Opcode == ARM::t2USATasr) && ShAmt == 0)
ShAmt = 32;
MI.addOperand(MCOperand::CreateImm(ShAmt));
if (ShAmt == 0) {
if (Opc == ARM_AM::asr)
ShAmt = 32;
else
Opc = ARM_AM::no_shift;
}
MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(Opc, ShAmt)));
}
return true;
}