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Eliminate CMPri, which is a synonym for SUBCCri
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24805 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -94,13 +94,6 @@ let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in {
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def RETL: F3_2<2, 0b111000, (ops),
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"retl", [(ret)]>;
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}
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// CMP is a special case of SUBCC where destination is ignored, by setting it to
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// %g0 (hardwired zero).
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// FIXME: should keep track of the fact that it defs the integer condition codes
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let rd = 0 in
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def CMPri: F3_2<2, 0b010100,
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(ops IntRegs:$b, i32imm:$c),
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"cmp $b, $c", []>;
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// Section B.1 - Load Integer Instructions, p. 90
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def LDSBrr : F3_1<3, 0b001001,
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@ -520,6 +513,8 @@ def FABSS : F3_3<2, 0b110100, 0b000001001,
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(ops FPRegs:$dst, FPRegs:$src),
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"fabss $src, $dst",
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[(set FPRegs:$dst, (fabs FPRegs:$src))]>;
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// FIXME: ADD FNEGD/FABSD pseudo instructions.
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// Floating-point Square Root Instructions, p.145
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def FSQRTS : F3_3<2, 0b110100, 0b000101001,
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@ -1062,7 +1062,7 @@ void V8ISel::visitBranchInst(BranchInst &I) {
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// CondReg=(<condition>);
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// If (CondReg==0) goto notTakenSuccMBB;
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unsigned CondReg = getReg (I.getCondition ());
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BuildMI (BB, V8::CMPri, 2).addSImm (0).addReg (CondReg);
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BuildMI (BB, V8::SUBCCri, 2, V8::G0).addReg(CondReg).addSImm(0);
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BuildMI (BB, V8::BE, 1).addMBB (notTakenSuccMBB);
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BuildMI (BB, V8::BA, 1).addMBB (takenSuccMBB);
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return;
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@ -1062,7 +1062,7 @@ void V8ISel::visitBranchInst(BranchInst &I) {
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// CondReg=(<condition>);
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// If (CondReg==0) goto notTakenSuccMBB;
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unsigned CondReg = getReg (I.getCondition ());
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BuildMI (BB, V8::CMPri, 2).addSImm (0).addReg (CondReg);
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BuildMI (BB, V8::SUBCCri, 2, V8::G0).addReg(CondReg).addSImm(0);
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BuildMI (BB, V8::BE, 1).addMBB (notTakenSuccMBB);
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BuildMI (BB, V8::BA, 1).addMBB (takenSuccMBB);
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return;
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@ -94,13 +94,6 @@ let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in {
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def RETL: F3_2<2, 0b111000, (ops),
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"retl", [(ret)]>;
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}
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// CMP is a special case of SUBCC where destination is ignored, by setting it to
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// %g0 (hardwired zero).
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// FIXME: should keep track of the fact that it defs the integer condition codes
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let rd = 0 in
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def CMPri: F3_2<2, 0b010100,
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(ops IntRegs:$b, i32imm:$c),
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"cmp $b, $c", []>;
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// Section B.1 - Load Integer Instructions, p. 90
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def LDSBrr : F3_1<3, 0b001001,
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@ -520,6 +513,8 @@ def FABSS : F3_3<2, 0b110100, 0b000001001,
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(ops FPRegs:$dst, FPRegs:$src),
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"fabss $src, $dst",
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[(set FPRegs:$dst, (fabs FPRegs:$src))]>;
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// FIXME: ADD FNEGD/FABSD pseudo instructions.
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// Floating-point Square Root Instructions, p.145
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def FSQRTS : F3_3<2, 0b110100, 0b000101001,
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