mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-22 09:29:31 +00:00
Improve code layout, mostly indentation.
No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119142 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Kalle Raiskila
parent
b46443a686
commit
38e0c9ba57
@ -559,98 +559,96 @@ LowerLOAD(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
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// Get pointerinfos to the memory chunk(s) that contain the data to load
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uint64_t mpi_offset = LN->getPointerInfo().Offset;
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mpi_offset -= mpi_offset%16;
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MachinePointerInfo lowMemPtr( LN->getPointerInfo().V, mpi_offset);
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MachinePointerInfo highMemPtr( LN->getPointerInfo().V, mpi_offset+16);
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MachinePointerInfo lowMemPtr(LN->getPointerInfo().V, mpi_offset);
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MachinePointerInfo highMemPtr(LN->getPointerInfo().V, mpi_offset+16);
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SDValue result;
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SDValue basePtr = LN->getBasePtr();
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SDValue rotate;
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if (alignment == 16) {
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ConstantSDNode *CN;
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SDValue result;
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SDValue basePtr = LN->getBasePtr();
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SDValue rotate;
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// Special cases for a known aligned load to simplify the base pointer
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// and the rotation amount:
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if (basePtr.getOpcode() == ISD::ADD
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&& (CN = dyn_cast<ConstantSDNode > (basePtr.getOperand(1))) != 0) {
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// Known offset into basePtr
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int64_t offset = CN->getSExtValue();
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int64_t rotamt = int64_t((offset & 0xf) - pso);
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if (alignment == 16) {
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ConstantSDNode *CN;
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if (rotamt < 0)
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rotamt += 16;
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// Special cases for a known aligned load to simplify the base pointer
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// and the rotation amount:
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if (basePtr.getOpcode() == ISD::ADD
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&& (CN = dyn_cast<ConstantSDNode > (basePtr.getOperand(1))) != 0) {
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// Known offset into basePtr
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int64_t offset = CN->getSExtValue();
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int64_t rotamt = int64_t((offset & 0xf) - pso);
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rotate = DAG.getConstant(rotamt, MVT::i16);
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if (rotamt < 0)
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rotamt += 16;
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rotate = DAG.getConstant(rotamt, MVT::i16);
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// Simplify the base pointer for this case:
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basePtr = basePtr.getOperand(0);
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if ((offset & ~0xf) > 0) {
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basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT,
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basePtr,
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DAG.getConstant((offset & ~0xf), PtrVT));
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}
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} else if ((basePtr.getOpcode() == SPUISD::AFormAddr)
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|| (basePtr.getOpcode() == SPUISD::IndirectAddr
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&& basePtr.getOperand(0).getOpcode() == SPUISD::Hi
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&& basePtr.getOperand(1).getOpcode() == SPUISD::Lo)) {
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// Plain aligned a-form address: rotate into preferred slot
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// Same for (SPUindirect (SPUhi ...), (SPUlo ...))
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int64_t rotamt = -pso;
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if (rotamt < 0)
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rotamt += 16;
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rotate = DAG.getConstant(rotamt, MVT::i16);
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} else {
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// Offset the rotate amount by the basePtr and the preferred slot
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// byte offset
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int64_t rotamt = -pso;
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if (rotamt < 0)
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rotamt += 16;
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rotate = DAG.getNode(ISD::ADD, dl, PtrVT,
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basePtr,
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DAG.getConstant(rotamt, PtrVT));
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}
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} else {
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// Unaligned load: must be more pessimistic about addressing modes:
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if (basePtr.getOpcode() == ISD::ADD) {
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MachineFunction &MF = DAG.getMachineFunction();
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MachineRegisterInfo &RegInfo = MF.getRegInfo();
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unsigned VReg = RegInfo.createVirtualRegister(&SPU::R32CRegClass);
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SDValue Flag;
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SDValue Op0 = basePtr.getOperand(0);
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SDValue Op1 = basePtr.getOperand(1);
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if (isa<ConstantSDNode>(Op1)) {
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// Convert the (add <ptr>, <const>) to an indirect address contained
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// in a register. Note that this is done because we need to avoid
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// creating a 0(reg) d-form address due to the SPU's block loads.
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basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Op0, Op1);
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the_chain = DAG.getCopyToReg(the_chain, dl, VReg, basePtr, Flag);
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basePtr = DAG.getCopyFromReg(the_chain, dl, VReg, PtrVT);
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} else {
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// Convert the (add <arg1>, <arg2>) to an indirect address, which
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// will likely be lowered as a reg(reg) x-form address.
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basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Op0, Op1);
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}
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} else {
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// Simplify the base pointer for this case:
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basePtr = basePtr.getOperand(0);
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if ((offset & ~0xf) > 0) {
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basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT,
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basePtr,
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DAG.getConstant(0, PtrVT));
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DAG.getConstant((offset & ~0xf), PtrVT));
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}
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} else if ((basePtr.getOpcode() == SPUISD::AFormAddr)
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|| (basePtr.getOpcode() == SPUISD::IndirectAddr
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&& basePtr.getOperand(0).getOpcode() == SPUISD::Hi
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&& basePtr.getOperand(1).getOpcode() == SPUISD::Lo)) {
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// Plain aligned a-form address: rotate into preferred slot
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// Same for (SPUindirect (SPUhi ...), (SPUlo ...))
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int64_t rotamt = -pso;
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if (rotamt < 0)
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rotamt += 16;
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rotate = DAG.getConstant(rotamt, MVT::i16);
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} else {
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// Offset the rotate amount by the basePtr and the preferred slot
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// byte offset
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int64_t rotamt = -pso;
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if (rotamt < 0)
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rotamt += 16;
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rotate = DAG.getNode(ISD::ADD, dl, PtrVT,
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basePtr,
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DAG.getConstant(-pso, PtrVT));
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DAG.getConstant(rotamt, PtrVT));
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}
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} else {
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// Unaligned load: must be more pessimistic about addressing modes:
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if (basePtr.getOpcode() == ISD::ADD) {
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MachineFunction &MF = DAG.getMachineFunction();
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MachineRegisterInfo &RegInfo = MF.getRegInfo();
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unsigned VReg = RegInfo.createVirtualRegister(&SPU::R32CRegClass);
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SDValue Flag;
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// Do the load as a i128 to allow possible shifting
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SDValue low = DAG.getLoad(MVT::i128, dl, the_chain, basePtr,
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lowMemPtr,
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LN->isVolatile(), LN->isNonTemporal(), 16);
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SDValue Op0 = basePtr.getOperand(0);
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SDValue Op1 = basePtr.getOperand(1);
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if (isa<ConstantSDNode>(Op1)) {
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// Convert the (add <ptr>, <const>) to an indirect address contained
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// in a register. Note that this is done because we need to avoid
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// creating a 0(reg) d-form address due to the SPU's block loads.
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basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Op0, Op1);
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the_chain = DAG.getCopyToReg(the_chain, dl, VReg, basePtr, Flag);
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basePtr = DAG.getCopyFromReg(the_chain, dl, VReg, PtrVT);
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} else {
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// Convert the (add <arg1>, <arg2>) to an indirect address, which
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// will likely be lowered as a reg(reg) x-form address.
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basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Op0, Op1);
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}
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} else {
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basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT,
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basePtr,
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DAG.getConstant(0, PtrVT));
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}
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// Offset the rotate amount by the basePtr and the preferred slot
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// byte offset
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rotate = DAG.getNode(ISD::ADD, dl, PtrVT,
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basePtr,
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DAG.getConstant(-pso, PtrVT));
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}
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// Do the load as a i128 to allow possible shifting
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SDValue low = DAG.getLoad(MVT::i128, dl, the_chain, basePtr,
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lowMemPtr,
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LN->isVolatile(), LN->isNonTemporal(), 16);
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// When the size is not greater than alignment we get all data with just
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// one load
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@ -675,16 +673,16 @@ LowerLOAD(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
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// extra kowledge, and might avoid the second load
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else {
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// storage position offset from lower 16 byte aligned memory chunk
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SDValue offset = DAG.getNode( ISD::AND, dl, MVT::i32,
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SDValue offset = DAG.getNode(ISD::AND, dl, MVT::i32,
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basePtr, DAG.getConstant( 0xf, MVT::i32 ) );
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// 16 - offset
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SDValue offset_compl = DAG.getNode( ISD::SUB, dl, MVT::i32,
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SDValue offset_compl = DAG.getNode(ISD::SUB, dl, MVT::i32,
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DAG.getConstant( 16, MVT::i32),
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offset );
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// get a registerfull of ones. (this implementation is a workaround: LLVM
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// cannot handle 128 bit signed int constants)
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SDValue ones = DAG.getConstant( -1, MVT::v4i32 );
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ones = DAG.getNode( ISD::BIT_CONVERT, dl, MVT::i128, ones);
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SDValue ones = DAG.getConstant(-1, MVT::v4i32 );
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ones = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i128, ones);
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SDValue high = DAG.getLoad(MVT::i128, dl, the_chain,
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DAG.getNode(ISD::ADD, dl, PtrVT,
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@ -699,22 +697,22 @@ LowerLOAD(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
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// Shift the (possible) high part right to compensate the misalignemnt.
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// if there is no highpart (i.e. value is i64 and offset is 4), this
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// will zero out the high value.
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high = DAG.getNode( SPUISD::SRL_BYTES, dl, MVT::i128, high,
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DAG.getNode( ISD::SUB, dl, MVT::i32,
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high = DAG.getNode(SPUISD::SRL_BYTES, dl, MVT::i128, high,
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DAG.getNode(ISD::SUB, dl, MVT::i32,
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DAG.getConstant( 16, MVT::i32),
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offset
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));
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// Shift the low similarily
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// TODO: add SPUISD::SHL_BYTES
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low = DAG.getNode( SPUISD::SHL_BYTES, dl, MVT::i128, low, offset );
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low = DAG.getNode(SPUISD::SHL_BYTES, dl, MVT::i128, low, offset );
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// Merge the two parts
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result = DAG.getNode( ISD::BIT_CONVERT, dl, vecVT,
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result = DAG.getNode(ISD::BIT_CONVERT, dl, vecVT,
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DAG.getNode(ISD::OR, dl, MVT::i128, low, high));
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if (!InVT.isVector()) {
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result = DAG.getNode( SPUISD::VEC2PREFSLOT, dl, InVT, result );
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result = DAG.getNode(SPUISD::VEC2PREFSLOT, dl, InVT, result );
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}
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}
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@ -764,8 +762,8 @@ LowerSTORE(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
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// Get pointerinfos to the memory chunk(s) that contain the data to load
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uint64_t mpi_offset = SN->getPointerInfo().Offset;
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mpi_offset -= mpi_offset%16;
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MachinePointerInfo lowMemPtr( SN->getPointerInfo().V, mpi_offset);
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MachinePointerInfo highMemPtr( SN->getPointerInfo().V, mpi_offset+16);
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MachinePointerInfo lowMemPtr(SN->getPointerInfo().V, mpi_offset);
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MachinePointerInfo highMemPtr(SN->getPointerInfo().V, mpi_offset+16);
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// two sanity checks
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@ -775,80 +773,78 @@ LowerSTORE(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
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if (StVT.getSizeInBits() == 128 && alignment == 16)
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return SDValue();
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SDValue alignLoadVec;
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SDValue basePtr = SN->getBasePtr();
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SDValue the_chain = SN->getChain();
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SDValue insertEltOffs;
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if (alignment == 16) {
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ConstantSDNode *CN;
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// Special cases for a known aligned load to simplify the base pointer
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// and insertion byte:
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if (basePtr.getOpcode() == ISD::ADD
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&& (CN = dyn_cast<ConstantSDNode>(basePtr.getOperand(1))) != 0) {
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// Known offset into basePtr
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int64_t offset = CN->getSExtValue();
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SDValue alignLoadVec;
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SDValue basePtr = SN->getBasePtr();
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SDValue the_chain = SN->getChain();
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SDValue insertEltOffs;
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// Simplify the base pointer for this case:
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basePtr = basePtr.getOperand(0);
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insertEltOffs = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT,
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basePtr,
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DAG.getConstant((offset & 0xf), PtrVT));
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if (alignment == 16) {
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ConstantSDNode *CN;
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// Special cases for a known aligned load to simplify the base pointer
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// and insertion byte:
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if (basePtr.getOpcode() == ISD::ADD
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&& (CN = dyn_cast<ConstantSDNode>(basePtr.getOperand(1))) != 0) {
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// Known offset into basePtr
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int64_t offset = CN->getSExtValue();
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// Simplify the base pointer for this case:
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basePtr = basePtr.getOperand(0);
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insertEltOffs = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT,
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basePtr,
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DAG.getConstant((offset & 0xf), PtrVT));
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if ((offset & ~0xf) > 0) {
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basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT,
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basePtr,
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DAG.getConstant((offset & ~0xf), PtrVT));
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}
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} else {
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// Otherwise, assume it's at byte 0 of basePtr
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insertEltOffs = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT,
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basePtr,
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DAG.getConstant(0, PtrVT));
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basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT,
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basePtr,
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DAG.getConstant(0, PtrVT));
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}
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} else {
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// Unaligned load: must be more pessimistic about addressing modes:
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if (basePtr.getOpcode() == ISD::ADD) {
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MachineFunction &MF = DAG.getMachineFunction();
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MachineRegisterInfo &RegInfo = MF.getRegInfo();
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unsigned VReg = RegInfo.createVirtualRegister(&SPU::R32CRegClass);
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SDValue Flag;
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SDValue Op0 = basePtr.getOperand(0);
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SDValue Op1 = basePtr.getOperand(1);
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if (isa<ConstantSDNode>(Op1)) {
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// Convert the (add <ptr>, <const>) to an indirect address contained
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// in a register. Note that this is done because we need to avoid
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// creating a 0(reg) d-form address due to the SPU's block loads.
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basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Op0, Op1);
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the_chain = DAG.getCopyToReg(the_chain, dl, VReg, basePtr, Flag);
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basePtr = DAG.getCopyFromReg(the_chain, dl, VReg, PtrVT);
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} else {
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// Convert the (add <arg1>, <arg2>) to an indirect address, which
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// will likely be lowered as a reg(reg) x-form address.
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basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Op0, Op1);
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}
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} else {
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if ((offset & ~0xf) > 0) {
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basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT,
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basePtr,
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DAG.getConstant(0, PtrVT));
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DAG.getConstant((offset & ~0xf), PtrVT));
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}
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// Insertion point is solely determined by basePtr's contents
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insertEltOffs = DAG.getNode(ISD::ADD, dl, PtrVT,
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} else {
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// Otherwise, assume it's at byte 0 of basePtr
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insertEltOffs = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT,
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basePtr,
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DAG.getConstant(0, PtrVT));
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basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT,
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basePtr,
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DAG.getConstant(0, PtrVT));
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}
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} else {
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// Unaligned load: must be more pessimistic about addressing modes:
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if (basePtr.getOpcode() == ISD::ADD) {
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MachineFunction &MF = DAG.getMachineFunction();
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MachineRegisterInfo &RegInfo = MF.getRegInfo();
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unsigned VReg = RegInfo.createVirtualRegister(&SPU::R32CRegClass);
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SDValue Flag;
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// Load the lower part of the memory to which to store.
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SDValue low = DAG.getLoad(vecVT, dl, the_chain, basePtr,
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lowMemPtr, SN->isVolatile(), SN->isNonTemporal(), 16);
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SDValue Op0 = basePtr.getOperand(0);
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SDValue Op1 = basePtr.getOperand(1);
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if (isa<ConstantSDNode>(Op1)) {
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// Convert the (add <ptr>, <const>) to an indirect address contained
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// in a register. Note that this is done because we need to avoid
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// creating a 0(reg) d-form address due to the SPU's block loads.
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basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Op0, Op1);
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the_chain = DAG.getCopyToReg(the_chain, dl, VReg, basePtr, Flag);
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basePtr = DAG.getCopyFromReg(the_chain, dl, VReg, PtrVT);
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} else {
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// Convert the (add <arg1>, <arg2>) to an indirect address, which
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// will likely be lowered as a reg(reg) x-form address.
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basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Op0, Op1);
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}
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} else {
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basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT,
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basePtr,
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DAG.getConstant(0, PtrVT));
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}
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// Insertion point is solely determined by basePtr's contents
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insertEltOffs = DAG.getNode(ISD::ADD, dl, PtrVT,
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basePtr,
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DAG.getConstant(0, PtrVT));
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}
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// Load the lower part of the memory to which to store.
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SDValue low = DAG.getLoad(vecVT, dl, the_chain, basePtr,
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lowMemPtr, SN->isVolatile(), SN->isNonTemporal(), 16);
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// if we don't need to store over the 16 byte boundary, one store suffices
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if (alignment >= StVT.getSizeInBits()/8) {
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@ -893,17 +889,6 @@ LowerSTORE(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
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LN->isVolatile(), LN->isNonTemporal(),
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16);
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|
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#if 0 && !defined(NDEBUG)
|
||||
if (DebugFlag && isCurrentDebugType(DEBUG_TYPE)) {
|
||||
const SDValue ¤tRoot = DAG.getRoot();
|
||||
|
||||
DAG.setRoot(result);
|
||||
errs() << "------- CellSPU:LowerStore result:\n";
|
||||
DAG.dump();
|
||||
errs() << "-------\n";
|
||||
DAG.setRoot(currentRoot);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
// do the store when it might cross the 16 byte memory access boundary.
|
||||
else {
|
||||
@ -1003,7 +988,6 @@ LowerSTORE(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
|
||||
}
|
||||
|
||||
return result;
|
||||
|
||||
}
|
||||
|
||||
//! Generate the address of a constant pool entry.
|
||||
|
||||
Loading…
Reference in New Issue
Block a user