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[fast-isel] Add support for ADDs with non-legal types.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149934 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chad Rosier 2012-02-06 23:50:07 +00:00
parent d0b3da1ea2
commit 3901c3e750
2 changed files with 74 additions and 5 deletions
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39
lib/Target/ARM/ARMFastISel.cpp
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@ -160,7 +160,8 @@ class ARMFastISel : public FastISel {
bool SelectCmp(const Instruction *I);
bool SelectFPExt(const Instruction *I);
bool SelectFPTrunc(const Instruction *I);
bool SelectBinaryOp(const Instruction *I, unsigned ISDOpcode);
bool SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode);
bool SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode);
bool SelectIToFP(const Instruction *I, bool isSigned);
bool SelectFPToI(const Instruction *I, bool isSigned);
bool SelectDiv(const Instruction *I, bool isSigned);
@ -1722,7 +1723,33 @@ bool ARMFastISel::SelectRem(const Instruction *I, bool isSigned) {
return ARMEmitLibcall(I, LC);
}
bool ARMFastISel::SelectBinaryOp(const Instruction *I, unsigned ISDOpcode) {
bool ARMFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) {
assert (ISDOpcode == ISD::ADD && "Expected an add.");
EVT DestVT = TLI.getValueType(I->getType(), true);
// We can get here in the case when we have a binary operation on a non-legal
// type and the target independent selector doesn't know how to handle it.
if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
return false;
unsigned SrcReg1 = getRegForValue(I->getOperand(0));
if (SrcReg1 == 0) return false;
// TODO: Often the 2nd operand is an immediate, which can be encoded directly
// in the instruction, rather then materializing the value in a register.
unsigned SrcReg2 = getRegForValue(I->getOperand(1));
if (SrcReg2 == 0) return false;
unsigned Opc = isThumb2 ? ARM::t2ADDrr : ARM::ADDrr;
unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::i32));
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
TII.get(Opc), ResultReg)
.addReg(SrcReg1).addReg(SrcReg2));
UpdateValueMap(I, ResultReg);
return true;
}
bool ARMFastISel::SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode) {
EVT VT = TLI.getValueType(I->getType(), true);
// We can get here in the case when we want to use NEON for our fp
@ -2458,12 +2485,14 @@ bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
return SelectFPToI(I, /*isSigned*/ true);
case Instruction::FPToUI:
return SelectFPToI(I, /*isSigned*/ false);
case Instruction::Add:
return SelectBinaryIntOp(I, ISD::ADD);
case Instruction::FAdd:
return SelectBinaryOp(I, ISD::FADD);
return SelectBinaryFPOp(I, ISD::FADD);
case Instruction::FSub:
return SelectBinaryOp(I, ISD::FSUB);
return SelectBinaryFPOp(I, ISD::FSUB);
case Instruction::FMul:
return SelectBinaryOp(I, ISD::FMUL);
return SelectBinaryFPOp(I, ISD::FMUL);
case Instruction::SDiv:
return SelectDiv(I, /*isSigned*/ true);
case Instruction::UDiv:

40
test/CodeGen/ARM/fast-isel-binary.ll Normal file
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@ -0,0 +1,40 @@
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
; Test add with non-legal types
define void @add_i1(i1 %a, i1 %b) nounwind ssp {
entry:
; ARM: add_i1
; THUMB: add_i1
%a.addr = alloca i1, align 4
%0 = add i1 %a, %b
; ARM: add r0, r0, r1
; THUMB: add r0, r1
store i1 %0, i1* %a.addr, align 4
ret void
}
define void @add_i8(i8 %a, i8 %b) nounwind ssp {
entry:
; ARM: add_i8
; THUMB: add_i8
%a.addr = alloca i8, align 4
%0 = add i8 %a, %b
; ARM: add r0, r0, r1
; THUMB: add r0, r1
store i8 %0, i8* %a.addr, align 4
ret void
}
define void @add_i16(i16 %a, i16 %b) nounwind ssp {
entry:
; ARM: add_i16
; THUMB: add_i16
%a.addr = alloca i16, align 4
%0 = add i16 %a, %b
; ARM: add r0, r0, r1
; THUMB: add r0, r1
store i16 %0, i16* %a.addr, align 4
ret void
}