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Remove non-DebugLoc forms of the exotic forms

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of Lod and Sto; patch uses.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63716 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dale Johannesen 2009-02-04 02:34:38 +00:00
parent 4715f6395e
commit 39355f9fea
6 changed files with 91 additions and 178 deletions
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11
include/llvm/CodeGen/SelectionDAG.h
View File

@ -582,16 +582,10 @@ public:
SDValue getLoad(MVT VT, DebugLoc dl, SDValue Chain, SDValue Ptr,
const Value *SV, int SVOffset, bool isVolatile=false,
unsigned Alignment=0);
SDValue getExtLoad(ISD::LoadExtType ExtType, MVT VT,
SDValue Chain, SDValue Ptr, const Value *SV,
int SVOffset, MVT EVT, bool isVolatile=false,
unsigned Alignment=0);
SDValue getExtLoad(ISD::LoadExtType ExtType, DebugLoc dl, MVT VT,
SDValue Chain, SDValue Ptr, const Value *SV,
int SVOffset, MVT EVT, bool isVolatile=false,
unsigned Alignment=0);
SDValue getIndexedLoad(SDValue OrigLoad, SDValue Base,
SDValue Offset, ISD::MemIndexedMode AM);
SDValue getIndexedLoad(SDValue OrigLoad, DebugLoc dl, SDValue Base,
SDValue Offset, ISD::MemIndexedMode AM);
SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
@ -613,14 +607,9 @@ public:
SDValue getStore(SDValue Chain, DebugLoc dl, SDValue Val, SDValue Ptr,
const Value *SV, int SVOffset, bool isVolatile=false,
unsigned Alignment=0);
SDValue getTruncStore(SDValue Chain, SDValue Val, SDValue Ptr,
const Value *SV, int SVOffset, MVT TVT,
bool isVolatile=false, unsigned Alignment=0);
SDValue getTruncStore(SDValue Chain, DebugLoc dl, SDValue Val, SDValue Ptr,
const Value *SV, int SVOffset, MVT TVT,
bool isVolatile=false, unsigned Alignment=0);
SDValue getIndexedStore(SDValue OrigStoe, SDValue Base,
SDValue Offset, ISD::MemIndexedMode AM);
SDValue getIndexedStore(SDValue OrigStoe, DebugLoc dl, SDValue Base,
SDValue Offset, ISD::MemIndexedMode AM);

3
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

@ -585,7 +585,8 @@ static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
if (Extend)
return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, DAG.getEntryNode(),
return DAG.getExtLoad(ISD::EXTLOAD, CFP->getDebugLoc(),
OrigVT, DAG.getEntryNode(),
CPIdx, PseudoSourceValue::getConstantPool(),
0, VT, false, Alignment);
return DAG.getLoad(OrigVT, DAG.getEntryNode(), CPIdx,

82
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -3669,16 +3669,6 @@ SDValue SelectionDAG::getLoad(MVT VT, DebugLoc dl,
SV, SVOffset, VT, isVolatile, Alignment);
}
SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, MVT VT,
SDValue Chain, SDValue Ptr,
const Value *SV,
int SVOffset, MVT EVT,
bool isVolatile, unsigned Alignment) {
SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType());
return getLoad(ISD::UNINDEXED, ExtType, VT, Chain, Ptr, Undef,
SV, SVOffset, EVT, isVolatile, Alignment);
}
SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, DebugLoc dl, MVT VT,
SDValue Chain, SDValue Ptr,
const Value *SV,
@ -3689,18 +3679,6 @@ SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, DebugLoc dl, MVT VT,
SV, SVOffset, EVT, isVolatile, Alignment);
}
SDValue
SelectionDAG::getIndexedLoad(SDValue OrigLoad, SDValue Base,
SDValue Offset, ISD::MemIndexedMode AM) {
LoadSDNode *LD = cast<LoadSDNode>(OrigLoad);
assert(LD->getOffset().getOpcode() == ISD::UNDEF &&
"Load is already a indexed load!");
return getLoad(AM, LD->getExtensionType(), OrigLoad.getValueType(),
LD->getChain(), Base, Offset, LD->getSrcValue(),
LD->getSrcValueOffset(), LD->getMemoryVT(),
LD->isVolatile(), LD->getAlignment());
}
SDValue
SelectionDAG::getIndexedLoad(SDValue OrigLoad, DebugLoc dl, SDValue Base,
SDValue Offset, ISD::MemIndexedMode AM) {
@ -3767,41 +3745,6 @@ SDValue SelectionDAG::getStore(SDValue Chain, DebugLoc dl, SDValue Val,
return SDValue(N, 0);
}
SDValue SelectionDAG::getTruncStore(SDValue Chain, SDValue Val,
SDValue Ptr, const Value *SV,
int SVOffset, MVT SVT,
bool isVolatile, unsigned Alignment) {
MVT VT = Val.getValueType();
if (VT == SVT)
return getStore(Chain, Val, Ptr, SV, SVOffset, isVolatile, Alignment);
assert(VT.bitsGT(SVT) && "Not a truncation?");
assert(VT.isInteger() == SVT.isInteger() &&
"Can't do FP-INT conversion!");
if (Alignment == 0) // Ensure that codegen never sees alignment 0
Alignment = getMVTAlignment(VT);
SDVTList VTs = getVTList(MVT::Other);
SDValue Undef = getNode(ISD::UNDEF, Ptr.getValueType());
SDValue Ops[] = { Chain, Val, Ptr, Undef };
FoldingSetNodeID ID;
AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4);
ID.AddInteger(SVT.getRawBits());
ID.AddInteger(encodeMemSDNodeFlags(true, ISD::UNINDEXED,
isVolatile, Alignment));
void *IP = 0;
if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
return SDValue(E, 0);
SDNode *N = NodeAllocator.Allocate<StoreSDNode>();
new (N) StoreSDNode(Ops, VTs, ISD::UNINDEXED, true,
SVT, SV, SVOffset, Alignment, isVolatile);
CSEMap.InsertNode(N, IP);
AllNodes.push_back(N);
return SDValue(N, 0);
}
SDValue SelectionDAG::getTruncStore(SDValue Chain, DebugLoc dl, SDValue Val,
SDValue Ptr, const Value *SV,
int SVOffset, MVT SVT,
@ -3837,31 +3780,6 @@ SDValue SelectionDAG::getTruncStore(SDValue Chain, DebugLoc dl, SDValue Val,
return SDValue(N, 0);
}
SDValue
SelectionDAG::getIndexedStore(SDValue OrigStore, SDValue Base,
SDValue Offset, ISD::MemIndexedMode AM) {
StoreSDNode *ST = cast<StoreSDNode>(OrigStore);
assert(ST->getOffset().getOpcode() == ISD::UNDEF &&
"Store is already a indexed store!");
SDVTList VTs = getVTList(Base.getValueType(), MVT::Other);
SDValue Ops[] = { ST->getChain(), ST->getValue(), Base, Offset };
FoldingSetNodeID ID;
AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4);
ID.AddInteger(ST->getMemoryVT().getRawBits());
ID.AddInteger(ST->getRawSubclassData());
void *IP = 0;
if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
return SDValue(E, 0);
SDNode *N = NodeAllocator.Allocate<StoreSDNode>();
new (N) StoreSDNode(Ops, VTs, AM,
ST->isTruncatingStore(), ST->getMemoryVT(),
ST->getSrcValue(), ST->getSrcValueOffset(),
ST->getAlignment(), ST->isVolatile());
CSEMap.InsertNode(N, IP);
AllNodes.push_back(N);
return SDValue(N, 0);
}
SDValue
SelectionDAG::getIndexedStore(SDValue OrigStore, DebugLoc dl, SDValue Base,
SDValue Offset, ISD::MemIndexedMode AM) {

24
lib/Target/Alpha/AlphaISelLowering.cpp
View File

@ -461,6 +461,7 @@ void AlphaTargetLowering::LowerVAARG(SDNode *N, SDValue &Chain,
/// LowerOperation - Provide custom lowering hooks for some operations.
///
SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
DebugLoc dl = Op.getNode()->getDebugLoc();
switch (Op.getOpcode()) {
default: assert(0 && "Wasn't expecting to be able to lower this!");
case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG,
@ -573,10 +574,10 @@ SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
SDValue Result;
if (Op.getValueType() == MVT::i32)
Result = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Chain, DataPtr,
Result = DAG.getExtLoad(ISD::SEXTLOAD, dl, MVT::i64, Chain, DataPtr,
NULL, 0, MVT::i32);
else
Result = DAG.getLoad(Op.getValueType(), Chain, DataPtr, NULL, 0);
Result = DAG.getLoad(Op.getValueType(), dl, Chain, DataPtr, NULL, 0);
return Result;
}
case ISD::VACOPY: {
@ -586,14 +587,15 @@ SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
const Value *DestS = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
const Value *SrcS = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
SDValue Val = DAG.getLoad(getPointerTy(), Chain, SrcP, SrcS, 0);
SDValue Result = DAG.getStore(Val.getValue(1), Val, DestP, DestS, 0);
SDValue NP = DAG.getNode(ISD::ADD, MVT::i64, SrcP,
SDValue Val = DAG.getLoad(getPointerTy(), dl, Chain, SrcP, SrcS, 0);
SDValue Result = DAG.getStore(Val.getValue(1), dl, Val, DestP, DestS, 0);
SDValue NP = DAG.getNode(ISD::ADD, dl, MVT::i64, SrcP,
DAG.getConstant(8, MVT::i64));
Val = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Result, NP, NULL,0, MVT::i32);
SDValue NPD = DAG.getNode(ISD::ADD, MVT::i64, DestP,
Val = DAG.getExtLoad(ISD::SEXTLOAD, dl, MVT::i64, Result,
NP, NULL,0, MVT::i32);
SDValue NPD = DAG.getNode(ISD::ADD, dl, MVT::i64, DestP,
DAG.getConstant(8, MVT::i64));
return DAG.getTruncStore(Val.getValue(1), Val, NPD, NULL, 0, MVT::i32);
return DAG.getTruncStore(Val.getValue(1), dl, Val, NPD, NULL, 0, MVT::i32);
}
case ISD::VASTART: {
SDValue Chain = Op.getOperand(0);
@ -602,10 +604,10 @@ SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
// vastart stores the address of the VarArgsBase and VarArgsOffset
SDValue FR = DAG.getFrameIndex(VarArgsBase, MVT::i64);
SDValue S1 = DAG.getStore(Chain, FR, VAListP, VAListS, 0);
SDValue SA2 = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
SDValue S1 = DAG.getStore(Chain, dl, FR, VAListP, VAListS, 0);
SDValue SA2 = DAG.getNode(ISD::ADD, dl, MVT::i64, VAListP,
DAG.getConstant(8, MVT::i64));
return DAG.getTruncStore(S1, DAG.getConstant(VarArgsOffset, MVT::i64),
return DAG.getTruncStore(S1, dl, DAG.getConstant(VarArgsOffset, MVT::i64),
SA2, NULL, 0, MVT::i32);
}
case ISD::RETURNADDR:

105
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -1399,6 +1399,7 @@ PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
SmallVector<SDValue, 8> ArgValues;
SDValue Root = Op.getOperand(0);
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
DebugLoc dl = Op.getNode()->getDebugLoc();
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
bool isPPC64 = PtrVT == MVT::i64;
@ -1551,8 +1552,8 @@ PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
if (GPR_idx != Num_GPR_Regs) {
unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
RegInfo.addLiveIn(GPR[GPR_idx], VReg);
SDValue Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
SDValue Store = DAG.getTruncStore(Val.getValue(1), Val, FIN,
SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, PtrVT);
SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
NULL, 0, ObjSize==1 ? MVT::i8 : MVT::i16 );
MemOps.push_back(Store);
++GPR_idx;
@ -1571,8 +1572,8 @@ PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
RegInfo.addLiveIn(GPR[GPR_idx], VReg);
int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset);
SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
SDValue Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
SDValue Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, PtrVT);
SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
MemOps.push_back(Store);
++GPR_idx;
if (isMachoABI) ArgOffset += PtrByteSize;
@ -1594,7 +1595,7 @@ PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
if (GPR_idx != Num_GPR_Regs) {
unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
RegInfo.addLiveIn(GPR[GPR_idx], VReg);
ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32);
ArgVal = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32);
++GPR_idx;
} else {
needsLoad = true;
@ -1612,19 +1613,19 @@ PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
if (GPR_idx != Num_GPR_Regs) {
unsigned VReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass);
RegInfo.addLiveIn(GPR[GPR_idx], VReg);
ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i64);
ArgVal = DAG.getCopyFromReg(Root, dl, VReg, MVT::i64);
if (ObjectVT == MVT::i32) {
// PPC64 passes i8, i16, and i32 values in i64 registers. Promote
// value to MVT::i64 and then truncate to the correct register size.
if (Flags.isSExt())
ArgVal = DAG.getNode(ISD::AssertSext, MVT::i64, ArgVal,
ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
DAG.getValueType(ObjectVT));
else if (Flags.isZExt())
ArgVal = DAG.getNode(ISD::AssertZext, MVT::i64, ArgVal,
ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
DAG.getValueType(ObjectVT));
ArgVal = DAG.getNode(ISD::TRUNCATE, MVT::i32, ArgVal);
ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
}
++GPR_idx;
@ -1652,7 +1653,7 @@ PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
else
VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
RegInfo.addLiveIn(FPR[FPR_idx], VReg);
ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
ArgVal = DAG.getCopyFromReg(Root, dl, VReg, ObjectVT);
++FPR_idx;
} else {
needsLoad = true;
@ -1673,7 +1674,7 @@ PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
if (VR_idx != Num_VR_Regs) {
unsigned VReg = RegInfo.createVirtualRegister(&PPC::VRRCRegClass);
RegInfo.addLiveIn(VR[VR_idx], VReg);
ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
ArgVal = DAG.getCopyFromReg(Root, dl, VReg, ObjectVT);
if (isVarArg) {
while ((ArgOffset % 16) != 0) {
ArgOffset += PtrByteSize;
@ -1707,7 +1708,7 @@ PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
CurArgOffset + (ArgSize - ObjSize),
isImmutable);
SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
ArgVal = DAG.getLoad(ObjectVT, dl, Root, FIN, NULL, 0);
}
ArgValues.push_back(ArgVal);
@ -1763,11 +1764,11 @@ PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
if (isELF32_ABI) {
for (GPR_idx = 0; GPR_idx != VarArgsNumGPR; ++GPR_idx) {
SDValue Val = DAG.getRegister(GPR[GPR_idx], PtrVT);
SDValue Store = DAG.getStore(Root, Val, FIN, NULL, 0);
SDValue Store = DAG.getStore(Root, dl, Val, FIN, NULL, 0);
MemOps.push_back(Store);
// Increment the address by four for the next argument to store
SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
}
}
@ -1782,12 +1783,12 @@ PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
RegInfo.addLiveIn(GPR[GPR_idx], VReg);
SDValue Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
SDValue Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, PtrVT);
SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
MemOps.push_back(Store);
// Increment the address by four for the next argument to store
SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
}
// In ELF 32 ABI, the double arguments are stored to the VarArgsFrameIndex
@ -1795,12 +1796,12 @@ PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
if (isELF32_ABI) {
for (FPR_idx = 0; FPR_idx != VarArgsNumFPR; ++FPR_idx) {
SDValue Val = DAG.getRegister(FPR[FPR_idx], MVT::f64);
SDValue Store = DAG.getStore(Root, Val, FIN, NULL, 0);
SDValue Store = DAG.getStore(Root, dl, Val, FIN, NULL, 0);
MemOps.push_back(Store);
// Increment the address by eight for the next argument to store
SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8,
PtrVT);
FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
}
for (; FPR_idx != Num_FPR_Regs; ++FPR_idx) {
@ -1808,24 +1809,25 @@ PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
RegInfo.addLiveIn(FPR[FPR_idx], VReg);
SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::f64);
SDValue Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::f64);
SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
MemOps.push_back(Store);
// Increment the address by eight for the next argument to store
SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8,
PtrVT);
FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
}
}
}
if (!MemOps.empty())
Root = DAG.getNode(ISD::TokenFactor, MVT::Other,&MemOps[0],MemOps.size());
Root = DAG.getNode(ISD::TokenFactor, dl,
MVT::Other, &MemOps[0], MemOps.size());
ArgValues.push_back(Root);
// Return the new list of results.
return DAG.getNode(ISD::MERGE_VALUES, Op.getNode()->getVTList(),
return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
&ArgValues[0], ArgValues.size());
}
@ -2223,13 +2225,13 @@ SDValue PPCTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG,
else
PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, PtrOff);
PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
// On PPC64, promote integers to 64-bit values.
if (isPPC64 && Arg.getValueType() == MVT::i32) {
// FIXME: Should this use ANY_EXTEND if neither sext nor zext?
unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
Arg = DAG.getNode(ExtOp, MVT::i64, Arg);
Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
}
// FIXME Elf untested, what are alignment rules?
@ -2242,7 +2244,7 @@ SDValue PPCTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG,
// Everything else is passed left-justified.
MVT VT = (Size==1) ? MVT::i8 : MVT::i16;
if (GPR_idx != NumGPRs) {
SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, PtrVT, Chain, Arg,
SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
NULL, 0, VT);
MemOpChains.push_back(Load.getValue(1));
RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
@ -2250,7 +2252,7 @@ SDValue PPCTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG,
ArgOffset += PtrByteSize;
} else {
SDValue Const = DAG.getConstant(4 - Size, PtrOff.getValueType());
SDValue AddPtr = DAG.getNode(ISD::ADD, PtrVT, PtrOff, Const);
SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr,
CallSeqStart.getNode()->getOperand(0),
Flags, DAG, Size, dl);
@ -2278,9 +2280,9 @@ SDValue PPCTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG,
// And copy the pieces of it that fit into registers.
for (unsigned j=0; j<Size; j+=PtrByteSize) {
SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
SDValue AddArg = DAG.getNode(ISD::ADD, PtrVT, Arg, Const);
SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
if (GPR_idx != NumGPRs) {
SDValue Load = DAG.getLoad(PtrVT, Chain, AddArg, NULL, 0);
SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg, NULL, 0);
MemOpChains.push_back(Load.getValue(1));
RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
if (isMachoABI)
@ -2321,20 +2323,20 @@ SDValue PPCTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG,
RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
if (isVarArg) {
SDValue Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0);
SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0);
MemOpChains.push_back(Store);
// Float varargs are always shadowed in available integer registers
if (GPR_idx != NumGPRs) {
SDValue Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, NULL, 0);
MemOpChains.push_back(Load.getValue(1));
if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++],
Load));
}
if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
PtrOff = DAG.getNode(ISD::ADD, PtrVT, PtrOff, ConstFour);
SDValue Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, NULL, 0);
MemOpChains.push_back(Load.getValue(1));
if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++],
Load));
@ -2384,12 +2386,12 @@ SDValue PPCTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG,
}
// We could elide this store in the case where the object fits
// entirely in R registers. Maybe later.
PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr,
PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
DAG.getConstant(ArgOffset, PtrVT));
SDValue Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0);
SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0);
MemOpChains.push_back(Store);
if (VR_idx != NumVRs) {
SDValue Load = DAG.getLoad(MVT::v4f32, Store, PtrOff, NULL, 0);
SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff, NULL, 0);
MemOpChains.push_back(Load.getValue(1));
RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
}
@ -2397,9 +2399,9 @@ SDValue PPCTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG,
for (unsigned i=0; i<16; i+=PtrByteSize) {
if (GPR_idx == NumGPRs)
break;
SDValue Ix = DAG.getNode(ISD::ADD, PtrVT, PtrOff,
SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
DAG.getConstant(i, PtrVT));
SDValue Load = DAG.getLoad(PtrVT, Store, Ix, NULL, 0);
SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, NULL, 0);
MemOpChains.push_back(Load.getValue(1));
RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
}
@ -2449,22 +2451,22 @@ SDValue PPCTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG,
}
if (!MemOpChains.empty())
Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&MemOpChains[0], MemOpChains.size());
// Build a sequence of copy-to-reg nodes chained together with token chain
// and flag operands which copy the outgoing args into the appropriate regs.
SDValue InFlag;
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
InFlag);
Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
RegsToPass[i].second, InFlag);
InFlag = Chain.getValue(1);
}
// With the ELF 32 ABI, set CR6 to true if this is a vararg call.
if (isVarArg && isELF32_ABI) {
SDValue SetCR(DAG.getTargetNode(PPC::CRSET, MVT::i32), 0);
Chain = DAG.getCopyToReg(Chain, PPC::CR1EQ, SetCR, InFlag);
SDValue SetCR(DAG.getTargetNode(PPC::CRSET, dl, MVT::i32), 0);
Chain = DAG.getCopyToReg(Chain, dl, PPC::CR1EQ, SetCR, InFlag);
InFlag = Chain.getValue(1);
}
@ -2477,7 +2479,7 @@ SDValue PPCTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG,
StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
MemOpChains2);
if (!MemOpChains2.empty())
Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&MemOpChains2[0], MemOpChains2.size());
// Store the return address to the appropriate stack slot.
@ -2520,14 +2522,14 @@ SDValue PPCTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG,
// Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
// to do the call, we can't use PPCISD::CALL.
SDValue MTCTROps[] = {Chain, Callee, InFlag};
Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, MTCTROps,
Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps,
2 + (InFlag.getNode() != 0));
InFlag = Chain.getValue(1);
// Copy the callee address into R12/X12 on darwin.
if (isMachoABI) {
unsigned Reg = Callee.getValueType() == MVT::i32 ? PPC::R12 : PPC::X12;
Chain = DAG.getCopyToReg(Chain, Reg, Callee, InFlag);
Chain = DAG.getCopyToReg(Chain, dl, Reg, Callee, InFlag);
InFlag = Chain.getValue(1);
}
@ -2570,12 +2572,12 @@ SDValue PPCTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG,
if (isTailCall) {
assert(InFlag.getNode() &&
"Flag must be set. Depend on flag being set in LowerRET");
Chain = DAG.getNode(PPCISD::TAILCALL,
Chain = DAG.getNode(PPCISD::TAILCALL, dl,
TheCall->getVTList(), &Ops[0], Ops.size());
return SDValue(Chain.getNode(), Op.getResNo());
}
Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size());
Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
InFlag = Chain.getValue(1);
Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
@ -2595,7 +2597,8 @@ SDValue PPCTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG,
CCValAssign &VA = RVLocs[i];
MVT VT = VA.getValVT();
assert(VA.isRegLoc() && "Can only return in registers!");
Chain = DAG.getCopyFromReg(Chain, VA.getLocReg(), VT, InFlag).getValue(1);
Chain = DAG.getCopyFromReg(Chain, dl,
VA.getLocReg(), VT, InFlag).getValue(1);
ResultVals.push_back(Chain.getValue(0));
InFlag = Chain.getValue(2);
}
@ -2606,7 +2609,7 @@ SDValue PPCTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG,
// Otherwise, merge everything together with a MERGE_VALUES node.
ResultVals.push_back(Chain);
SDValue Res = DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(),
SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(),
&ResultVals[0], ResultVals.size());
return Res.getValue(Op.getResNo());
}

44
lib/Target/Sparc/SparcISelLowering.cpp
View File

@ -103,16 +103,16 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
case MVT::i32:
if (I->use_empty()) { // Argument is dead.
if (CurArgReg < ArgRegEnd) ++CurArgReg;
ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
ArgValues.push_back(DAG.getNode(ISD::UNDEF, dl, ObjectVT));
} else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
MF.getRegInfo().addLiveIn(*CurArgReg++, VReg);
SDValue Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
SDValue Arg = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32);
if (ObjectVT != MVT::i32) {
unsigned AssertOp = ISD::AssertSext;
Arg = DAG.getNode(AssertOp, MVT::i32, Arg,
Arg = DAG.getNode(AssertOp, dl, MVT::i32, Arg,
DAG.getValueType(ObjectVT));
Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg);
Arg = DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, Arg);
}
ArgValues.push_back(Arg);
} else {
@ -120,17 +120,17 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
SDValue Load;
if (ObjectVT == MVT::i32) {
Load = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
Load = DAG.getLoad(MVT::i32, dl, Root, FIPtr, NULL, 0);
} else {
ISD::LoadExtType LoadOp = ISD::SEXTLOAD;
// Sparc is big endian, so add an offset based on the ObjectVT.
unsigned Offset = 4-std::max(1U, ObjectVT.getSizeInBits()/8);
FIPtr = DAG.getNode(ISD::ADD, MVT::i32, FIPtr,
FIPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIPtr,
DAG.getConstant(Offset, MVT::i32));
Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr,
Load = DAG.getExtLoad(LoadOp, dl, MVT::i32, Root, FIPtr,
NULL, 0, ObjectVT);
Load = DAG.getNode(ISD::TRUNCATE, ObjectVT, Load);
Load = DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, Load);
}
ArgValues.push_back(Load);
}
@ -140,19 +140,19 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
case MVT::f32:
if (I->use_empty()) { // Argument is dead.
if (CurArgReg < ArgRegEnd) ++CurArgReg;
ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
ArgValues.push_back(DAG.getNode(ISD::UNDEF, dl, ObjectVT));
} else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
// FP value is passed in an integer register.
unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
MF.getRegInfo().addLiveIn(*CurArgReg++, VReg);
SDValue Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
SDValue Arg = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32);
Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg);
Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Arg);
ArgValues.push_back(Arg);
} else {
int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
SDValue Load = DAG.getLoad(MVT::f32, Root, FIPtr, NULL, 0);
SDValue Load = DAG.getLoad(MVT::f32, dl, Root, FIPtr, NULL, 0);
ArgValues.push_back(Load);
}
ArgOffset += 4;
@ -163,37 +163,37 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
if (I->use_empty()) { // Argument is dead.
if (CurArgReg < ArgRegEnd) ++CurArgReg;
if (CurArgReg < ArgRegEnd) ++CurArgReg;
ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
ArgValues.push_back(DAG.getNode(ISD::UNDEF, dl, ObjectVT));
} else {
SDValue HiVal;
if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
MF.getRegInfo().addLiveIn(*CurArgReg++, VRegHi);
HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32);
HiVal = DAG.getCopyFromReg(Root, dl, VRegHi, MVT::i32);
} else {
int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
HiVal = DAG.getLoad(MVT::i32, dl, Root, FIPtr, NULL, 0);
}
SDValue LoVal;
if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
unsigned VRegLo = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
MF.getRegInfo().addLiveIn(*CurArgReg++, VRegLo);
LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32);
LoVal = DAG.getCopyFromReg(Root, dl, VRegLo, MVT::i32);
} else {
int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4);
SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
LoVal = DAG.getLoad(MVT::i32, dl, Root, FIPtr, NULL, 0);
}
// Compose the two halves together into an i64 unit.
SDValue WholeValue =
DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal);
DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
// If we want a double, do a bit convert.
if (ObjectVT == MVT::f64)
WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue);
WholeValue = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, WholeValue);
ArgValues.push_back(WholeValue);
}
@ -210,18 +210,18 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
MF.getRegInfo().addLiveIn(*CurArgReg, VReg);
SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32);
int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
OutChains.push_back(DAG.getStore(DAG.getRoot(), Arg, FIPtr, NULL, 0));
OutChains.push_back(DAG.getStore(DAG.getRoot(), dl, Arg, FIPtr, NULL, 0));
ArgOffset += 4;
}
}
if (!OutChains.empty())
DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
DAG.setRoot(DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
&OutChains[0], OutChains.size()));
}