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Use fconsts and fconstd to materialize small fp constants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85362 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -3990,3 +3990,60 @@ ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
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// The ARM target isn't yet aware of offsets.
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return false;
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}
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int ARM::getVFPf32Imm(const APFloat &FPImm) {
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APInt Imm = FPImm.bitcastToAPInt();
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uint32_t Sign = Imm.lshr(31).getZExtValue() & 1;
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int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127
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int64_t Mantissa = Imm.getZExtValue() & 0x7fffff; // 23 bits
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// We can handle 4 bits of mantissa.
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// mantissa = (16+UInt(e:f:g:h))/16.
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if (Mantissa & 0x7ffff)
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return -1;
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Mantissa >>= 19;
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if ((Mantissa & 0xf) != Mantissa)
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return -1;
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// We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
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if (Exp < -3 || Exp > 4)
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return -1;
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Exp = ((Exp+3) & 0x7) ^ 4;
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return ((int)Sign << 7) | (Exp << 4) | Mantissa;
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}
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int ARM::getVFPf64Imm(const APFloat &FPImm) {
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APInt Imm = FPImm.bitcastToAPInt();
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uint64_t Sign = Imm.lshr(63).getZExtValue() & 1;
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int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023
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uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffLL;
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// We can handle 4 bits of mantissa.
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// mantissa = (16+UInt(e:f:g:h))/16.
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if (Mantissa & 0xffffffffffffLL)
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return -1;
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Mantissa >>= 48;
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if ((Mantissa & 0xf) != Mantissa)
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return -1;
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// We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
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if (Exp < -3 || Exp > 4)
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return -1;
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Exp = ((Exp+3) & 0x7) ^ 4;
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return ((int)Sign << 7) | (Exp << 4) | Mantissa;
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}
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/// isFPImmLegal - Returns true if the target can instruction select the
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/// specified FP immediate natively. If false, the legalizer will
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/// materialize the FP immediate as a load from a constant pool.
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bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
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if (!Subtarget->hasVFP3())
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return false;
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if (VT == MVT::f32)
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return ARM::getVFPf32Imm(Imm) != -1;
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if (VT == MVT::f64)
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return ARM::getVFPf64Imm(Imm) != -1;
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return false;
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}
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@ -137,6 +137,13 @@ namespace llvm {
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/// return the constant being splatted. The ByteSize field indicates the
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/// number of bytes of each element [1248].
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SDValue getVMOVImm(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
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/// getVFPf32Imm / getVFPf64Imm - If the given fp immediate can be
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/// materialized with a VMOV.f32 / VMOV.f64 (i.e. fconsts / fconstd)
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/// instruction, returns its 8-bit integer representation. Otherwise,
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/// returns -1.
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int getVFPf32Imm(const APFloat &FPImm);
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int getVFPf64Imm(const APFloat &FPImm);
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}
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//===--------------------------------------------------------------------===//
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@ -224,6 +231,12 @@ namespace llvm {
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bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const;
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bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
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/// isFPImmLegal - Returns true if the target can instruction select the
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/// specified FP immediate natively. If false, the legalizer will
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/// materialize the FP immediate as a load from a constant pool.
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virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
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private:
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/// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
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/// make the right decision when generating code for different targets.
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@ -30,6 +30,26 @@ def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutFlag]>;
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def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0",SDT_CMPFP0, [SDNPOutFlag]>;
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def arm_fmdrr : SDNode<"ARMISD::FMDRR", SDT_FMDRR>;
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//===----------------------------------------------------------------------===//
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// Operand Definitions.
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//
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def vfp_f32imm : Operand<f32>,
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PatLeaf<(f32 fpimm), [{
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return ARM::getVFPf32Imm(N->getValueAPF()) != -1;
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}]> {
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let PrintMethod = "printVFPf32ImmOperand";
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}
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def vfp_f64imm : Operand<f64>,
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PatLeaf<(f64 fpimm), [{
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return ARM::getVFPf64Imm(N->getValueAPF()) != -1;
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}]> {
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let PrintMethod = "printVFPf64ImmOperand";
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}
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//===----------------------------------------------------------------------===//
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// Load / store Instructions.
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//
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@ -408,3 +428,27 @@ def FMSTAT : VFPAI<(outs), (ins), VFPMiscFrm, IIC_fpSTAT, "fmstat", "",
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let Inst{7} = 0;
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let Inst{4} = 1;
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}
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// Materialize FP immediates. VFP3 only.
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def FCONSTS : VFPAI<(outs SPR:$dst), (ins vfp_f32imm:$imm),
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VFPMiscFrm, IIC_VMOVImm,
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"fconsts", "\t$dst, $imm",
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[(set SPR:$dst, vfp_f32imm:$imm)]>, Requires<[HasVFP3]> {
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let Inst{27-23} = 0b11101;
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let Inst{21-20} = 0b11;
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let Inst{11-9} = 0b101;
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let Inst{8} = 0;
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let Inst{7-4} = 0b0000;
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}
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def FCONSTD : VFPAI<(outs DPR:$dst), (ins vfp_f64imm:$imm),
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VFPMiscFrm, IIC_VMOVImm,
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"fconstd", "\t$dst, $imm",
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[(set DPR:$dst, vfp_f64imm:$imm)]>, Requires<[HasVFP3]> {
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let Inst{27-23} = 0b11101;
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let Inst{21-20} = 0b11;
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let Inst{11-9} = 0b101;
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let Inst{8} = 1;
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let Inst{7-4} = 0b0000;
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}
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@ -135,6 +135,8 @@ namespace {
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void printJT2BlockOperand(const MachineInstr *MI, int OpNum);
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void printTBAddrMode(const MachineInstr *MI, int OpNum);
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void printNoHashImmediate(const MachineInstr *MI, int OpNum);
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void printVFPf32ImmOperand(const MachineInstr *MI, int OpNum);
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void printVFPf64ImmOperand(const MachineInstr *MI, int OpNum);
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virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
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unsigned AsmVariant, const char *ExtraCode);
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@ -393,9 +395,11 @@ static void printSOImm(formatted_raw_ostream &O, int64_t V, bool VerboseAsm,
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if (Rot) {
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O << "#" << Imm << ", " << Rot;
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// Pretty printed version.
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if (VerboseAsm)
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O << ' ' << MAI->getCommentString()
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<< ' ' << (int)ARM_AM::rotr32(Imm, Rot);
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if (VerboseAsm) {
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O.PadToColumn(MAI->getCommentColumn());
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O << MAI->getCommentString() << ' ';
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O << (int)ARM_AM::rotr32(Imm, Rot);
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}
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} else {
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O << "#" << Imm;
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}
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@ -970,6 +974,26 @@ void ARMAsmPrinter::printNoHashImmediate(const MachineInstr *MI, int OpNum) {
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O << MI->getOperand(OpNum).getImm();
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}
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void ARMAsmPrinter::printVFPf32ImmOperand(const MachineInstr *MI, int OpNum) {
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const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
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O << ARM::getVFPf32Imm(FP->getValueAPF());
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if (VerboseAsm) {
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O.PadToColumn(MAI->getCommentColumn());
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O << MAI->getCommentString() << ' ';
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WriteAsOperand(O, FP, /*PrintType=*/false);
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}
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}
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void ARMAsmPrinter::printVFPf64ImmOperand(const MachineInstr *MI, int OpNum) {
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const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
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O << ARM::getVFPf64Imm(FP->getValueAPF());
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if (VerboseAsm) {
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O.PadToColumn(MAI->getCommentColumn());
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O << MAI->getCommentString() << ' ';
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WriteAsOperand(O, FP, /*PrintType=*/false);
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}
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}
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bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
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unsigned AsmVariant, const char *ExtraCode){
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// Does this asm operand have a single letter operand modifier?
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@ -1182,7 +1206,8 @@ void ARMAsmPrinter::PrintGlobalVariable(const GlobalVariable* GVar) {
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EmitAlignment(Align, GVar);
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O << name << ":";
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if (VerboseAsm) {
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O << "\t\t\t\t" << MAI->getCommentString() << ' ';
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O.PadToColumn(MAI->getCommentColumn());
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O << MAI->getCommentString() << ' ';
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WriteAsOperand(O, GVar, /*PrintType=*/false, GVar->getParent());
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}
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O << '\n';
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@ -1205,7 +1230,8 @@ void ARMAsmPrinter::PrintGlobalVariable(const GlobalVariable* GVar) {
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O << "," << (MAI->getAlignmentIsInBytes() ? (1 << Align) : Align);
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}
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if (VerboseAsm) {
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O << "\t\t" << MAI->getCommentString() << " ";
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O.PadToColumn(MAI->getCommentColumn());
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O << MAI->getCommentString() << ' ';
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WriteAsOperand(O, GVar, /*PrintType=*/false, GVar->getParent());
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}
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O << "\n";
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@ -1243,7 +1269,8 @@ void ARMAsmPrinter::PrintGlobalVariable(const GlobalVariable* GVar) {
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EmitAlignment(Align, GVar);
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O << name << ":";
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if (VerboseAsm) {
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O << "\t\t\t\t" << MAI->getCommentString() << " ";
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O.PadToColumn(MAI->getCommentColumn());
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O << MAI->getCommentString() << ' ';
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WriteAsOperand(O, GVar, /*PrintType=*/false, GVar->getParent());
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}
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O << "\n";
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@ -78,6 +78,8 @@ public:
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void printJT2BlockOperand(const MCInst *MI, unsigned OpNum) {}
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void printTBAddrMode(const MCInst *MI, unsigned OpNum) {}
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void printNoHashImmediate(const MCInst *MI, unsigned OpNum);
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void printVFPf32ImmOperand(const MCInst *MI, int OpNum) {}
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void printVFPf64ImmOperand(const MCInst *MI, int OpNum) {}
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void printPCLabel(const MCInst *MI, unsigned OpNum);
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// FIXME: Implement.
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33
test/CodeGen/ARM/fpconsts.ll
Normal file
33
test/CodeGen/ARM/fpconsts.ll
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@ -0,0 +1,33 @@
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; RUN: llc < %s -march=arm -mattr=+vfp3 | FileCheck %s
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define arm_apcscc float @t1(float %x) nounwind readnone optsize {
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entry:
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; CHECK: t1:
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; CHECK: fconsts s1, 16
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%0 = fadd float %x, 4.000000e+00
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ret float %0
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}
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define arm_apcscc double @t2(double %x) nounwind readnone optsize {
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entry:
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; CHECK: t2:
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; CHECK: fconstd d1, 8
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%0 = fadd double %x, 3.000000e+00
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ret double %0
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}
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define arm_apcscc double @t3(double %x) nounwind readnone optsize {
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entry:
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; CHECK: t3:
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; CHECK: fconstd d1, 170
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%0 = fmul double %x, -1.300000e+01
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ret double %0
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}
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define arm_apcscc float @t4(float %x) nounwind readnone optsize {
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entry:
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; CHECK: t4:
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; CHECK: fconsts s1, 184
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%0 = fmul float %x, -2.400000e+01
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ret float %0
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}
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