6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-06-10 15:29:52 +00:00
Code Issues Projects Releases Wiki Activity

Move the Target way of overriding DAG Scheduler to a target hook

Browse Source 
Summary:
The previous way of overriding it was relying on calling "setDefault"
on the global registry, which implies global mutable state.

Reviewers: echristo, atrick

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11538

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243388 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Mehdi Amini 2015-07-28 06:18:04 +00:00
parent 268011e5e2
commit 3942a2979d
3 changed files with 12 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
include/llvm/CodeGen/SchedulerRegistry.h
View File

@ -52,12 +52,6 @@ public:
static RegisterScheduler *getList() {
return (RegisterScheduler *)Registry.getList();
}
static FunctionPassCtor getDefault() {
return (FunctionPassCtor)Registry.getDefault();
}
static void setDefault(FunctionPassCtor C) {
Registry.setDefault((MachinePassCtor)C);
}
static void setListener(MachinePassRegistryListener *L) {
Registry.setListener(L);
}

6
include/llvm/Target/TargetSubtargetInfo.h
View File

@ -15,6 +15,7 @@
#define LLVM_TARGET_TARGETSUBTARGETINFO_H
#include "llvm/CodeGen/PBQPRAConstraint.h"
#include "llvm/CodeGen/SchedulerRegistry.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/Support/CodeGen.h"
@ -81,6 +82,11 @@ public:
virtual const TargetSelectionDAGInfo *getSelectionDAGInfo() const {
return nullptr;
}
/// Target can subclass this hook to select a different DAG scheduler.
virtual RegisterScheduler::FunctionPassCtor
getDAGScheduler(CodeGenOpt::Level) const {
return nullptr;
}
/// getRegisterInfo - If register information is available, return it. If
/// not, return null. This is kept separate from RegInfo until RegInfo has

14
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -293,6 +293,11 @@ namespace llvm {
const TargetLowering *TLI = IS->TLI;
const TargetSubtargetInfo &ST = IS->MF->getSubtarget();
// Try first to see if the Target has its own way of selecting a scheduler
if (auto *SchedulerCtor = ST.getDAGScheduler(OptLevel)) {
return SchedulerCtor(IS, OptLevel);
}
if (OptLevel == CodeGenOpt::None ||
(ST.enableMachineScheduler() && ST.enableMachineSchedDefaultSched()) ||
TLI->getSchedulingPreference() == Sched::Source)
@ -1643,14 +1648,7 @@ SelectionDAGISel::FinishBasicBlock() {
/// one preferred by the target.
///
ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
if (!Ctor) {
Ctor = ISHeuristic;
RegisterScheduler::setDefault(Ctor);
}
return Ctor(this, OptLevel);
return ISHeuristic(this, OptLevel);
}
//===----------------------------------------------------------------------===//